a_dpfifo_83p.tdf

91c111芯片的网络模块的原理图以及和ep1c6fpga连线相关的例子程序

--a_dpfifo ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" lpm_width=8 lpm_widthu=6 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" clock data empty full q rreq sclr usedw wreq lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO"
--VERSION_BEGIN 5.1 cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:11:08:14:10:50:SJ cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_fifo_common 2005:07:21:10:40:24:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_counter 2005:08:23:15:49:38:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_lpm_mux 2005:12:13:16:24:06:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_scfifo 2005:09:06:13:25:24:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ  VERSION_END


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FUNCTION a_fefifo_7cf (aclr, clock, rreq, sclr, wreq)
RETURNS ( empty, full, usedw_out[5..0]);
FUNCTION dpram_75p (data[7..0], inclock, outclock, outclocken, rdaddress[5..0], wraddress[5..0], wren)
RETURNS ( q[7..0]);
FUNCTION cntr_rd8 (aclr, clock, cnt_en, sclr)
RETURNS ( q[5..0]);

--synthesis_resources = lut 14 M4K 8 
SUBDESIGN a_dpfifo_83p
( 
	clock	:	input;
	data[7..0]	:	input;
	empty	:	output;
	full	:	output;
	q[7..0]	:	output;
	rreq	:	input;
	sclr	:	input;
	usedw[5..0]	:	output;
	wreq	:	input;
) 
VARIABLE 
	fifo_state : a_fefifo_7cf;
	FIFOram : dpram_75p;
	rd_ptr_count : cntr_rd8;
	wr_ptr : cntr_rd8;
	aclr	: NODE;
	rd_ptr[5..0]	: WIRE;
	valid_rreq	: WIRE;
	valid_wreq	: WIRE;

BEGIN 
	fifo_state.aclr = aclr;
	fifo_state.clock = clock;
	fifo_state.rreq = rreq;
	fifo_state.sclr = sclr;
	fifo_state.wreq = wreq;
	FIFOram.data[] = data[];
	FIFOram.inclock = clock;
	FIFOram.outclock = clock;
	FIFOram.outclocken = (valid_rreq # sclr);
	FIFOram.rdaddress[] = ((! sclr) & rd_ptr[]);
	FIFOram.wraddress[] = wr_ptr.q[];
	FIFOram.wren = valid_wreq;
	rd_ptr_count.aclr = aclr;
	rd_ptr_count.clock = clock;
	rd_ptr_count.cnt_en = valid_rreq;
	rd_ptr_count.sclr = sclr;
	wr_ptr.aclr = aclr;
	wr_ptr.clock = clock;
	wr_ptr.cnt_en = valid_wreq;
	wr_ptr.sclr = sclr;
	aclr = GND;
	empty = fifo_state.empty;
	full = fifo_state.full;
	q[] = FIFOram.q[];
	rd_ptr[] = rd_ptr_count.q[];
	usedw[] = fifo_state.usedw_out[];
	valid_rreq = rreq;
	valid_wreq = wreq;
END;
--VALID FILE