📄 altsyncram_arv1.tdf
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--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" INIT_FILE="cpu_0_ociram_default_contents.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=8 WIDTHAD_B=8 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" address_a address_b byteena_a clock0 clock1 clocken0 clocken1 data_a data_b q_a q_b wren_a wren_b
--VERSION_BEGIN 5.1 cbx_altsyncram 2005:11:08:14:10:50:SJ cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_lpm_mux 2005:12:13:16:24:06:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ VERSION_END
-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
PARAMETERS
(
PORT_A_ADDRESS_WIDTH = 1,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_DATA_WIDTH = 1,
PORT_B_ADDRESS_WIDTH = 1,
PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_B_DATA_WIDTH = 1
);
FUNCTION cyclone_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH, PORT_A_BYTE_ENABLE_CLEAR, PORT_A_BYTE_ENABLE_MASK_WIDTH, PORT_A_DATA_IN_CLEAR, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_WRITE_ENABLE_CLEAR, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH, PORT_B_BYTE_ENABLE_CLEAR, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH, PORT_B_DATA_IN_CLEAR, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = M4K 32
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_arv1
(
address_a[7..0] : input;
address_b[7..0] : input;
byteena_a[3..0] : input;
clock0 : input;
clock1 : input;
clocken0 : input;
clocken1 : input;
data_a[31..0] : input;
data_b[31..0] : input;
q_a[31..0] : output;
q_b[31..0] : output;
wren_a : input;
wren_b : input;
)
VARIABLE
ram_block1a0 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "cpu_0_ociram_default_contents.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 8,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 8,
PORT_B_DATA_IN_CLEAR = "none",
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 255,
PORT_B_LOGICAL_RAM_DEPTH = 256,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a1 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "cpu_0_ociram_default_contents.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 8,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 8,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 8,
PORT_B_DATA_IN_CLEAR = "none",
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 8,
PORT_B_LAST_ADDRESS = 255,
PORT_B_LOGICAL_RAM_DEPTH = 256,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a2 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "cpu_0_ociram_default_contents.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 8,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 16,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 8,
PORT_B_DATA_IN_CLEAR = "none",
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 16,
PORT_B_LAST_ADDRESS = 255,
PORT_B_LOGICAL_RAM_DEPTH = 256,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a3 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "cpu_0_ociram_default_contents.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 8,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 24,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 8,
PORT_B_DATA_IN_CLEAR = "none",
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 8,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 24,
PORT_B_LAST_ADDRESS = 255,
PORT_B_LOGICAL_RAM_DEPTH = 256,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
address_a_wire[7..0] : WIRE;
address_b_wire[7..0] : WIRE;
BEGIN
ram_block1a[3..0].clk0 = clock0;
ram_block1a[3..0].clk1 = clock1;
ram_block1a[3..0].ena0 = clocken0;
ram_block1a[3..0].ena1 = clocken1;
ram_block1a[3..0].portaaddr[] = ( address_a_wire[7..0]);
ram_block1a[0].portabyteenamasks[] = ( byteena_a[0..0]);
ram_block1a[1].portabyteenamasks[] = ( byteena_a[1..1]);
ram_block1a[2].portabyteenamasks[] = ( byteena_a[2..2]);
ram_block1a[3].portabyteenamasks[] = ( byteena_a[3..3]);
ram_block1a[0].portadatain[] = ( data_a[7..0]);
ram_block1a[1].portadatain[] = ( data_a[15..8]);
ram_block1a[2].portadatain[] = ( data_a[23..16]);
ram_block1a[3].portadatain[] = ( data_a[31..24]);
ram_block1a[3..0].portawe = wren_a;
ram_block1a[3..0].portbaddr[] = ( address_b_wire[7..0]);
ram_block1a[0].portbdatain[] = ( data_b[7..0]);
ram_block1a[1].portbdatain[] = ( data_b[15..8]);
ram_block1a[2].portbdatain[] = ( data_b[23..16]);
ram_block1a[3].portbdatain[] = ( data_b[31..24]);
ram_block1a[3..0].portbrewe = wren_b;
address_a_wire[] = address_a[];
address_b_wire[] = address_b[];
q_a[] = ( ram_block1a[3..0].portadataout[7..0]);
q_b[] = ( ram_block1a[3..0].portbdataout[7..0]);
END;
--VALID FILE
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