net_1c6_911.hier_info

91c111芯片的网络模块的原理图以及和ep1c6fpga连线相关的例子程序

clk => registered_cpu_0_data_master_readdata[6].CLK
clk => registered_cpu_0_data_master_readdata[5].CLK
clk => registered_cpu_0_data_master_readdata[4].CLK
clk => registered_cpu_0_data_master_readdata[3].CLK
clk => registered_cpu_0_data_master_readdata[2].CLK
clk => registered_cpu_0_data_master_readdata[1].CLK
clk => registered_cpu_0_data_master_readdata[0].CLK
clk => cpu_0_data_master_no_byte_enables_and_last_term~reg0.CLK
clk => dbs_16_reg_segment_0[15].CLK
clk => dbs_16_reg_segment_0[14].CLK
clk => dbs_16_reg_segment_0[13].CLK
clk => dbs_16_reg_segment_0[12].CLK
clk => dbs_16_reg_segment_0[11].CLK
clk => dbs_16_reg_segment_0[10].CLK
clk => dbs_16_reg_segment_0[9].CLK
clk => dbs_16_reg_segment_0[8].CLK
clk => dbs_16_reg_segment_0[7].CLK
clk => dbs_16_reg_segment_0[6].CLK
clk => dbs_16_reg_segment_0[5].CLK
clk => dbs_16_reg_segment_0[4].CLK
clk => dbs_16_reg_segment_0[3].CLK
clk => dbs_16_reg_segment_0[2].CLK
clk => dbs_16_reg_segment_0[1].CLK
clk => dbs_16_reg_segment_0[0].CLK
clk => cpu_0_data_master_dbs_address[1]~reg0.CLK
clk => cpu_0_data_master_dbs_address[0]~reg0.CLK
clk => dbs_8_reg_segment_0[7].CLK
clk => dbs_8_reg_segment_0[6].CLK
clk => dbs_8_reg_segment_0[5].CLK
clk => dbs_8_reg_segment_0[4].CLK
clk => dbs_8_reg_segment_0[3].CLK
clk => dbs_8_reg_segment_0[2].CLK
clk => dbs_8_reg_segment_0[1].CLK
clk => dbs_8_reg_segment_0[0].CLK
clk => dbs_8_reg_segment_1[7].CLK
clk => dbs_8_reg_segment_1[6].CLK
clk => dbs_8_reg_segment_1[5].CLK
clk => dbs_8_reg_segment_1[4].CLK
clk => dbs_8_reg_segment_1[3].CLK
clk => dbs_8_reg_segment_1[2].CLK
clk => dbs_8_reg_segment_1[1].CLK
clk => dbs_8_reg_segment_1[0].CLK
clk => dbs_8_reg_segment_2[7].CLK
clk => dbs_8_reg_segment_2[6].CLK
clk => dbs_8_reg_segment_2[5].CLK
clk => dbs_8_reg_segment_2[4].CLK
clk => dbs_8_reg_segment_2[3].CLK
clk => dbs_8_reg_segment_2[2].CLK
clk => dbs_8_reg_segment_2[1].CLK
clk => dbs_8_reg_segment_2[0].CLK
clk => cpu_0_data_master_waitrequest~reg0.CLK
cpu_0_data_master_address[0] => cpu_0_data_master_address_to_slave[0].DATAIN
cpu_0_data_master_address[1] => cpu_0_data_master_address_to_slave[1].DATAIN
cpu_0_data_master_address[2] => cpu_0_data_master_address_to_slave[2].DATAIN
cpu_0_data_master_address[3] => cpu_0_data_master_address_to_slave[3].DATAIN
cpu_0_data_master_address[4] => cpu_0_data_master_address_to_slave[4].DATAIN
cpu_0_data_master_address[5] => cpu_0_data_master_address_to_slave[5].DATAIN
cpu_0_data_master_address[6] => cpu_0_data_master_address_to_slave[6].DATAIN
cpu_0_data_master_address[7] => cpu_0_data_master_address_to_slave[7].DATAIN
cpu_0_data_master_address[8] => cpu_0_data_master_address_to_slave[8].DATAIN
cpu_0_data_master_address[9] => cpu_0_data_master_address_to_slave[9].DATAIN
cpu_0_data_master_address[10] => cpu_0_data_master_address_to_slave[10].DATAIN
cpu_0_data_master_address[11] => cpu_0_data_master_address_to_slave[11].DATAIN
cpu_0_data_master_address[12] => cpu_0_data_master_address_to_slave[12].DATAIN
cpu_0_data_master_address[13] => cpu_0_data_master_address_to_slave[13].DATAIN
cpu_0_data_master_address[14] => cpu_0_data_master_address_to_slave[14].DATAIN
cpu_0_data_master_address[15] => cpu_0_data_master_address_to_slave[15].DATAIN
cpu_0_data_master_address[16] => cpu_0_data_master_address_to_slave[16].DATAIN
cpu_0_data_master_address[17] => cpu_0_data_master_address_to_slave[17].DATAIN
cpu_0_data_master_address[18] => cpu_0_data_master_address_to_slave[18].DATAIN
cpu_0_data_master_address[19] => cpu_0_data_master_address_to_slave[19].DATAIN
cpu_0_data_master_address[20] => cpu_0_data_master_address_to_slave[20].DATAIN
cpu_0_data_master_address[21] => cpu_0_data_master_address_to_slave[21].DATAIN
cpu_0_data_master_address[22] => cpu_0_data_master_address_to_slave[22].DATAIN
cpu_0_data_master_address[23] => cpu_0_data_master_address_to_slave[23].DATAIN
cpu_0_data_master_byteenable_flash_s1 => pre_dbs_count_enable~9.IN0
cpu_0_data_master_byteenable_flash_s1 => last_dbs_term_and_run~3.IN0
cpu_0_data_master_byteenable_flash_s1 => r_1~31.IN1
cpu_0_data_master_byteenable_sdram_0_s1[0] => reduce_nor~0.IN1
cpu_0_data_master_byteenable_sdram_0_s1[1] => reduce_nor~0.IN0
cpu_0_data_master_debugaccess => ~NO_FANOUT~
cpu_0_data_master_granted_cpu_0_jtag_debug_module => r_0~1.IN1
cpu_0_data_master_granted_epcs_controller_epcs_control_port => r_0~9.IN1
cpu_0_data_master_granted_flash_s1 => r_1~39.IN0
cpu_0_data_master_granted_flash_s1 => pre_dbs_count_enable~12.IN1
cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave => ~NO_FANOUT~
cpu_0_data_master_granted_lan91c111_s1 => r_1~37.IN1
cpu_0_data_master_granted_led_pio_s1 => ~NO_FANOUT~
cpu_0_data_master_granted_sdram_0_s1 => r_1~0.IN0
cpu_0_data_master_granted_sdram_0_s1 => pre_dbs_count_enable~4.IN1
cpu_0_data_master_granted_sys_clk_timer_s1 => ~NO_FANOUT~
cpu_0_data_master_granted_sysid_control_slave => ~NO_FANOUT~
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module => r_0~0.IN1
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module => r_0~4.IN1
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module => r_0~1.IN0
cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port => r_0~7.IN1
cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port => r_0~12.IN1
cpu_0_data_master_qualified_request_epcs_controller_epcs_control_port => r_0~9.IN0
cpu_0_data_master_qualified_request_flash_s1 => r_1~30.IN1
cpu_0_data_master_qualified_request_flash_s1 => r_1~54.IN1
cpu_0_data_master_qualified_request_flash_s1 => r_1~49.IN1
cpu_0_data_master_qualified_request_flash_s1 => r_1~39.IN1
cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave => r_0~15.IN1
cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave => r_0~18.IN1
cpu_0_data_master_qualified_request_lan91c111_s1 => r_1~25.IN0
cpu_0_data_master_qualified_request_lan91c111_s1 => r_1~45.IN1
cpu_0_data_master_qualified_request_lan91c111_s1 => r_1~41.IN1
cpu_0_data_master_qualified_request_lan91c111_s1 => r_1~37.IN0
cpu_0_data_master_qualified_request_led_pio_s1 => r_0~23.IN1
cpu_0_data_master_qualified_request_led_pio_s1 => r_0~28.IN1
cpu_0_data_master_qualified_request_led_pio_s1 => r_0~25.IN1
cpu_0_data_master_qualified_request_sdram_0_s1 => r_0~31.IN1
cpu_0_data_master_qualified_request_sdram_0_s1 => r_1~6.IN1
cpu_0_data_master_qualified_request_sdram_0_s1 => r_1~1.IN1
cpu_0_data_master_qualified_request_sdram_0_s1 => r_1~0.IN1
cpu_0_data_master_qualified_request_sys_clk_timer_s1 => r_1~11.IN1
cpu_0_data_master_qualified_request_sys_clk_timer_s1 => r_1~16.IN1
cpu_0_data_master_qualified_request_sys_clk_timer_s1 => r_1~13.IN1
cpu_0_data_master_qualified_request_sysid_control_slave => r_1~22.IN1
cpu_0_data_master_qualified_request_sysid_control_slave => r_1~19.IN1
cpu_0_data_master_read => r_0~19.IN1
cpu_0_data_master_read => r_0~26.IN0
cpu_0_data_master_read => r_1~3.IN0
cpu_0_data_master_read => r_1~14.IN0
cpu_0_data_master_read => r_1~20.IN0
cpu_0_data_master_read => r_1~42.IN0
cpu_0_data_master_read => r_1~51.IN0
cpu_0_data_master_read => r_1~49.IN0
cpu_0_data_master_read => r_1~41.IN0
cpu_0_data_master_read => r_1~19.IN0
cpu_0_data_master_read => r_1~13.IN0
cpu_0_data_master_read => r_1~1.IN0
cpu_0_data_master_read => r_0~25.IN0
cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_epcs_controller_epcs_control_port => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_flash_s1 => pre_dbs_count_enable~11.IN1
cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_lan91c111_s1 => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_led_pio_s1 => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_sdram_0_s1 => r_1~2.IN1
cpu_0_data_master_read_data_valid_sdram_0_s1 => pre_dbs_count_enable~3.IN1
cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_sys_clk_timer_s1 => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_sysid_control_slave => ~NO_FANOUT~
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~0.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~1.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~2.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~3.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~4.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~5.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~6.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~7.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~8.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~9.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~10.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~11.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~12.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~13.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~14.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~15.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~16.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~17.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~18.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~19.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~20.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~21.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~22.IN0