net_1c6_911.hier_info

91c111芯片的网络模块的原理图以及和ep1c6fpga连线相关的例子程序

tri_state_bridge_0_address[5] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[6] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[7] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[8] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[9] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[10] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[11] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[12] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[13] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[14] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[15] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[16] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[17] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[18] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[19] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[20] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_byteenablen[0] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_byteenablen
tri_state_bridge_0_byteenablen[1] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_byteenablen
tri_state_bridge_0_byteenablen[2] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_byteenablen
tri_state_bridge_0_byteenablen[3] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_byteenablen
tri_state_bridge_0_data[0] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[1] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[2] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[3] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[4] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[5] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[6] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[7] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[8] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[9] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[10] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[11] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[12] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[13] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[14] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[15] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[16] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[17] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[18] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[19] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[20] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[21] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[22] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[23] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[24] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[25] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[26] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[27] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[28] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[29] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[30] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[31] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_readn <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_readn
write_n_to_the_flash <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.write_n_to_the_flash


|net_1c6_911|nios_c6:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module
clk => cpu_0_jtag_debug_module_arb_share_counter[2].CLK
clk => cpu_0_jtag_debug_module_arb_share_counter[1].CLK
clk => cpu_0_jtag_debug_module_arb_share_counter[0].CLK
clk => cpu_0_jtag_debug_module_slavearbiterlockenable.CLK
clk => last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module.CLK
clk => last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module.CLK
clk => cpu_0_jtag_debug_module_saved_chosen_master_vector[1].CLK
clk => cpu_0_jtag_debug_module_saved_chosen_master_vector[0].CLK
clk => cpu_0_jtag_debug_module_arb_addend[1].CLK
clk => cpu_0_jtag_debug_module_arb_addend[0].CLK
clk => d1_cpu_0_jtag_debug_module_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_0_data_master_address_to_slave[2] => cpu_0_jtag_debug_module_address~8.DATAB
cpu_0_data_master_address_to_slave[3] => cpu_0_jtag_debug_module_address~7.DATAB
cpu_0_data_master_address_to_slave[4] => cpu_0_jtag_debug_module_address~6.DATAB
cpu_0_data_master_address_to_slave[5] => cpu_0_jtag_debug_module_address~5.DATAB
cpu_0_data_master_address_to_slave[6] => cpu_0_jtag_debug_module_address~4.DATAB
cpu_0_data_master_address_to_slave[7] => cpu_0_jtag_debug_module_address~3.DATAB
cpu_0_data_master_address_to_slave[8] => cpu_0_jtag_debug_module_address~2.DATAB
cpu_0_data_master_address_to_slave[9] => cpu_0_jtag_debug_module_address~1.DATAB
cpu_0_data_master_address_to_slave[10] => cpu_0_jtag_debug_module_address~0.DATAB
cpu_0_data_master_address_to_slave[11] => Equal~0.IN47
cpu_0_data_master_address_to_slave[12] => Equal~0.IN46
cpu_0_data_master_address_to_slave[13] => Equal~0.IN45
cpu_0_data_master_address_to_slave[14] => Equal~0.IN44
cpu_0_data_master_address_to_slave[15] => Equal~0.IN43
cpu_0_data_master_address_to_slave[16] => Equal~0.IN42
cpu_0_data_master_address_to_slave[17] => Equal~0.IN41
cpu_0_data_master_address_to_slave[18] => Equal~0.IN40
cpu_0_data_master_address_to_slave[19] => Equal~0.IN39
cpu_0_data_master_address_to_slave[20] => Equal~0.IN38
cpu_0_data_master_address_to_slave[21] => Equal~0.IN37
cpu_0_data_master_address_to_slave[22] => Equal~0.IN36
cpu_0_data_master_address_to_slave[23] => Equal~0.IN35
cpu_0_data_master_byteenable[0] => cpu_0_jtag_debug_module_byteenable~3.DATAB
cpu_0_data_master_byteenable[1] => cpu_0_jtag_debug_module_byteenable~2.DATAB
cpu_0_data_master_byteenable[2] => cpu_0_jtag_debug_module_byteenable~1.DATAB
cpu_0_data_master_byteenable[3] => cpu_0_jtag_debug_module_byteenable~0.DATAB
cpu_0_data_master_debugaccess => cpu_0_jtag_debug_module_debugaccess.DATAIN
cpu_0_data_master_read => cpu_0_data_master_requests_cpu_0_jtag_debug_module~0.IN0
cpu_0_data_master_read => cpu_0_jtag_debug_module_in_a_read_cycle~0.IN0
cpu_0_data_master_write => cpu_0_data_master_requests_cpu_0_jtag_debug_module~0.IN1
cpu_0_data_master_write => cpu_0_jtag_debug_module_write~0.IN0
cpu_0_data_master_write => cpu_0_jtag_debug_module_in_a_write_cycle.IN0
cpu_0_data_master_writedata[0] => cpu_0_jtag_debug_module_writedata[0].DATAIN
cpu_0_data_master_writedata[1] => cpu_0_jtag_debug_module_writedata[1].DATAIN
cpu_0_data_master_writedata[2] => cpu_0_jtag_debug_module_writedata[2].DATAIN
cpu_0_data_master_writedata[3] => cpu_0_jtag_debug_module_writedata[3].DATAIN
cpu_0_data_master_writedata[4] => cpu_0_jtag_debug_module_writedata[4].DATAIN
cpu_0_data_master_writedata[5] => cpu_0_jtag_debug_module_writedata[5].DATAIN
cpu_0_data_master_writedata[6] => cpu_0_jtag_debug_module_writedata[6].DATAIN
cpu_0_data_master_writedata[7] => cpu_0_jtag_debug_module_writedata[7].DATAIN
cpu_0_data_master_writedata[8] => cpu_0_jtag_debug_module_writedata[8].DATAIN
cpu_0_data_master_writedata[9] => cpu_0_jtag_debug_module_writedata[9].DATAIN
cpu_0_data_master_writedata[10] => cpu_0_jtag_debug_module_writedata[10].DATAIN
cpu_0_data_master_writedata[11] => cpu_0_jtag_debug_module_writedata[11].DATAIN
cpu_0_data_master_writedata[12] => cpu_0_jtag_debug_module_writedata[12].DATAIN
cpu_0_data_master_writedata[13] => cpu_0_jtag_debug_module_writedata[13].DATAIN
cpu_0_data_master_writedata[14] => cpu_0_jtag_debug_module_writedata[14].DATAIN
cpu_0_data_master_writedata[15] => cpu_0_jtag_debug_module_writedata[15].DATAIN
cpu_0_data_master_writedata[16] => cpu_0_jtag_debug_module_writedata[16].DATAIN
cpu_0_data_master_writedata[17] => cpu_0_jtag_debug_module_writedata[17].DATAIN
cpu_0_data_master_writedata[18] => cpu_0_jtag_debug_module_writedata[18].DATAIN
cpu_0_data_master_writedata[19] => cpu_0_jtag_debug_module_writedata[19].DATAIN
cpu_0_data_master_writedata[20] => cpu_0_jtag_debug_module_writedata[20].DATAIN
cpu_0_data_master_writedata[21] => cpu_0_jtag_debug_module_writedata[21].DATAIN
cpu_0_data_master_writedata[22] => cpu_0_jtag_debug_module_writedata[22].DATAIN
cpu_0_data_master_writedata[23] => cpu_0_jtag_debug_module_writedata[23].DATAIN
cpu_0_data_master_writedata[24] => cpu_0_jtag_debug_module_writedata[24].DATAIN
cpu_0_data_master_writedata[25] => cpu_0_jtag_debug_module_writedata[25].DATAIN
cpu_0_data_master_writedata[26] => cpu_0_jtag_debug_module_writedata[26].DATAIN
cpu_0_data_master_writedata[27] => cpu_0_jtag_debug_module_writedata[27].DATAIN
cpu_0_data_master_writedata[28] => cpu_0_jtag_debug_module_writedata[28].DATAIN
cpu_0_data_master_writedata[29] => cpu_0_jtag_debug_module_writedata[29].DATAIN
cpu_0_data_master_writedata[30] => cpu_0_jtag_debug_module_writedata[30].DATAIN
cpu_0_data_master_writedata[31] => cpu_0_jtag_debug_module_writedata[31].DATAIN
cpu_0_instruction_master_address_to_slave[0] => ~NO_FANOUT~
cpu_0_instruction_master_address_to_slave[1] => ~NO_FANOUT~
cpu_0_instruction_master_address_to_slave[2] => cpu_0_jtag_debug_module_address~8.DATAA
cpu_0_instruction_master_address_to_slave[3] => cpu_0_jtag_debug_module_address~7.DATAA
cpu_0_instruction_master_address_to_slave[4] => cpu_0_jtag_debug_module_address~6.DATAA
cpu_0_instruction_master_address_to_slave[5] => cpu_0_jtag_debug_module_address~5.DATAA
cpu_0_instruction_master_address_to_slave[6] => cpu_0_jtag_debug_module_address~4.DATAA
cpu_0_instruction_master_address_to_slave[7] => cpu_0_jtag_debug_module_address~3.DATAA
cpu_0_instruction_master_address_to_slave[8] => cpu_0_jtag_debug_module_address~2.DATAA
cpu_0_instruction_master_address_to_slave[9] => cpu_0_jtag_debug_module_address~1.DATAA
cpu_0_instruction_master_address_to_slave[10] => cpu_0_jtag_debug_module_address~0.DATAA
cpu_0_instruction_master_address_to_slave[11] => Equal~1.IN47
cpu_0_instruction_master_address_to_slave[12] => Equal~1.IN46
cpu_0_instruction_master_address_to_slave[13] => Equal~1.IN45
cpu_0_instruction_master_address_to_slave[14] => Equal~1.IN44
cpu_0_instruction_master_address_to_slave[15] => Equal~1.IN43
cpu_0_instruction_master_address_to_slave[16] => Equal~1.IN42
cpu_0_instruction_master_address_to_slave[17] => Equal~1.IN41
cpu_0_instruction_master_address_to_slave[18] => Equal~1.IN40
cpu_0_instruction_master_address_to_slave[19] => Equal~1.IN39
cpu_0_instruction_master_address_to_slave[20] => Equal~1.IN38
cpu_0_instruction_master_address_to_slave[21] => Equal~1.IN37
cpu_0_instruction_master_address_to_slave[22] => Equal~1.IN36
cpu_0_instruction_master_address_to_slave[23] => Equal~1.IN35
cpu_0_instruction_master_latency_counter[0] => Equal~2.IN63
cpu_0_instruction_master_latency_counter[1] => Equal~2.IN62
cpu_0_instruction_master_read => cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~0.IN0
cpu_0_instruction_master_read => cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~1.IN0
cpu_0_instruction_master_read => cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module~1.IN0
cpu_0_instruction_master_read => cpu_0_jtag_debug_module_in_a_read_cycle~1.IN0
cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register => cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module~0.IN1
cpu_0_jtag_debug_module_readdata[0] => cpu_0_jtag_debug_module_readdata_from_sa[0].DATAIN