net_1c6_911.tan.qmsg

91c111芯片的网络模块的原理图以及和ep1c6fpga连线相关的例子程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 register nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[13\] 100.49 MHz 9.951 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 100.49 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode_usr1\" and destination register \"nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[13\]\" (period= 9.951 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.680 ns + Longest register register " "Info: + Longest register to register delay is 9.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LC_X30_Y17_N1 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y17_N1; Fanout = 17; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 390 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.894 ns) + CELL(0.442 ns) 2.336 ns nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[35\]~4704 2 COMB LC_X21_Y17_N1 48 " "Info: 2: + IC(1.894 ns) + CELL(0.442 ns) = 2.336 ns; Loc. = LC_X21_Y17_N1; Fanout = 48; COMB Node = 'nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[35\]~4704'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "2.336 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4704 } "NODE_NAME" } "" } } { "cpu_0_jtag_debug_module.v" "" { Text "D:/Test/net_1c6_911/cpu_0_jtag_debug_module.v" 203 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.121 ns) + CELL(0.114 ns) 4.571 ns nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[14\]~4713 3 COMB LC_X19_Y17_N1 23 " "Info: 3: + IC(2.121 ns) + CELL(0.114 ns) = 4.571 ns; Loc. = LC_X19_Y17_N1; Fanout = 23; COMB Node = 'nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[14\]~4713'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "2.235 ns" { nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4704 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[14]~4713 } "NODE_NAME" } "" } } { "cpu_0_jtag_debug_module.v" "" { Text "D:/Test/net_1c6_911/cpu_0_jtag_debug_module.v" 203 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.127 ns) + CELL(0.114 ns) 7.812 ns nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4765 4 COMB LC_X16_Y17_N8 1 " "Info: 4: + IC(3.127 ns) + CELL(0.114 ns) = 7.812 ns; Loc. = LC_X16_Y17_N8; Fanout = 1; COMB Node = 'nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4765'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "3.241 ns" { nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[14]~4713 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4765 } "NODE_NAME" } "" } } { "cpu_0_jtag_debug_module.v" "" { Text "D:/Test/net_1c6_911/cpu_0_jtag_debug_module.v" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.406 ns) + CELL(0.442 ns) 8.660 ns nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4766 5 COMB LC_X16_Y17_N5 1 " "Info: 5: + IC(0.406 ns) + CELL(0.442 ns) = 8.660 ns; Loc. = LC_X16_Y17_N5; Fanout = 1; COMB Node = 'nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4766'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "0.848 ns" { nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4765 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4766 } "NODE_NAME" } "" } } { "cpu_0_jtag_debug_module.v" "" { Text "D:/Test/net_1c6_911/cpu_0_jtag_debug_module.v" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.413 ns) + CELL(0.607 ns) 9.680 ns nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[13\] 6 REG LC_X16_Y17_N7 2 " "Info: 6: + IC(0.413 ns) + CELL(0.607 ns) = 9.680 ns; Loc. = LC_X16_Y17_N7; Fanout = 2; REG Node = 'nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[13\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "1.020 ns" { nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4766 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] } "NODE_NAME" } "" } } { "cpu_0_jtag_debug_module.v" "" { Text "D:/Test/net_1c6_911/cpu_0_jtag_debug_module.v" 203 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.719 ns ( 17.76 % ) " "Info: Total cell delay = 1.719 ns ( 17.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.961 ns ( 82.24 % ) " "Info: Total interconnect delay = 7.961 ns ( 82.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "9.680 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4704 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[14]~4713 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4765 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4766 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.680 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4704 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[14]~4713 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4765 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4766 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] } { 0.000ns 1.894ns 2.121ns 3.127ns 0.406ns 0.413ns } { 0.000ns 0.442ns 0.114ns 0.114ns 0.442ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.010 ns - Smallest " "Info: - Smallest clock skew is -0.010 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.601 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.601 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 153 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 153; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.890 ns) + CELL(0.711 ns) 5.601 ns nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[13\] 2 REG LC_X16_Y17_N7 2 " "Info: 2: + IC(4.890 ns) + CELL(0.711 ns) = 5.601 ns; Loc. = LC_X16_Y17_N7; Fanout = 2; REG Node = 'nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[13\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "5.601 ns" { altera_internal_jtag~TCKUTAP nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] } "NODE_NAME" } "" } } { "cpu_0_jtag_debug_module.v" "" { Text "D:/Test/net_1c6_911/cpu_0_jtag_debug_module.v" 203 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 12.69 % ) " "Info: Total cell delay = 0.711 ns ( 12.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.890 ns ( 87.31 % ) " "Info: Total interconnect delay = 4.890 ns ( 87.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "5.601 ns" { altera_internal_jtag~TCKUTAP nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.601 ns" { altera_internal_jtag~TCKUTAP nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] } { 0.000ns 4.890ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.611 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.611 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 153 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 153; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.900 ns) + CELL(0.711 ns) 5.611 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 2 REG LC_X30_Y17_N1 17 " "Info: 2: + IC(4.900 ns) + CELL(0.711 ns) = 5.611 ns; Loc. = LC_X30_Y17_N1; Fanout = 17; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "5.611 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 390 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 12.67 % ) " "Info: Total cell delay = 0.711 ns ( 12.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns ( 87.33 % ) " "Info: Total interconnect delay = 4.900 ns ( 87.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "5.611 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.611 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 4.900ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "5.601 ns" { altera_internal_jtag~TCKUTAP nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.601 ns" { altera_internal_jtag~TCKUTAP nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] } { 0.000ns 4.890ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "5.611 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.611 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 4.900ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 390 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "cpu_0_jtag_debug_module.v" "" { Text "D:/Test/net_1c6_911/cpu_0_jtag_debug_module.v" 203 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "9.680 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4704 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[14]~4713 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4765 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4766 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.680 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4704 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[14]~4713 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4765 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4766 nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] } { 0.000ns 1.894ns 2.121ns 3.127ns 0.406ns 0.413ns } { 0.000ns 0.442ns 0.114ns 0.114ns 0.442ns 0.607ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "5.601 ns" { altera_internal_jtag~TCKUTAP nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.601 ns" { altera_internal_jtag~TCKUTAP nios_c6:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] } { 0.000ns 4.890ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "5.611 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.611 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 4.900ns } { 0.000ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "altera_internal_jtag~UPDATEUSER " "Info: No valid register-to-register data paths exist for clock \"altera_internal_jtag~UPDATEUSER\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 register nios_c6:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_saved_chosen_master_vector\[0\] register nios_c6:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_saved_chosen_master_vector\[0\] 822 ps " "Info: Minimum slack time is 822 ps for clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" between source register \"nios_c6:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_saved_chosen_master_vector\[0\]\" and destination register \"nios_c6:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_saved_chosen_master_vector\[0\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.613 ns + Shortest register register " "Info: + Shortest register to register delay is 0.613 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns nios_c6:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_saved_chosen_master_vector\[0\] 1 REG LC_X13_Y12_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y12_N4; Fanout = 2; REG Node = 'nios_c6:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_saved_chosen_master_vector\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { nios_c6:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_saved_chosen_master_vector[0] } "NODE_NAME" } "" } } { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 294 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.613 ns) 0.613 ns nios_c6:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_saved_chosen_master_vector\[0\] 2 REG LC_X13_Y12_N4 2 " "Info: 2: + IC(0.000 ns) + CELL(0.613 ns) = 0.613 ns; Loc. = LC_X13_Y12_N4; Fanout = 2; REG Node = 'nios_c6:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_saved_chosen_master_vector\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "0.613 ns" { nios_c6:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_saved_chosen_master_vector[0] nios_c6:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_saved_chosen_master_vector[0] } "NODE_NAME" } "" } } { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 294 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.613 ns ( 100.00 % ) " "Info: Total cell delay = 0.613 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D