net_1c6_911.tan.qmsg

91c111芯片的网络模块的原理图以及和ep1c6fpga连线相关的例子程序

{ "Info" "ITDB_FULL_SLACK_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 register nios_c6:inst\|sdram_0_s1_arbitrator:the_sdram_0_s1\|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1\|fifo_contains_ones_n register nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[7\] 2.645 ns " "Info: Slack time is 2.645 ns for clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" between source register \"nios_c6:inst\|sdram_0_s1_arbitrator:the_sdram_0_s1\|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1\|fifo_contains_ones_n\" and destination register \"nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[7\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "57.62 MHz 17.355 ns " "Info: Fmax is 57.62 MHz (period= 17.355 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.024 ns + Largest register register " "Info: + Largest register to register requirement is 19.024 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 18.115 ns " "Info: + Latch edge is 18.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst1\|altpll:altpll_component\|_clk0 20.000 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 20.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst1\|altpll:altpll_component\|_clk0 20.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 20.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.300 ns + Largest " "Info: + Largest clock skew is -0.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 destination 2.046 ns + Shortest register " "Info: + Shortest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.046 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 2330 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 2330; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 765 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.827 ns) + CELL(0.219 ns) 2.046 ns nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[7\] 2 REG IOC_X8_Y21_N1 1 " "Info: 2: + IC(1.827 ns) + CELL(0.219 ns) = 2.046 ns; Loc. = IOC_X8_Y21_N1; Fanout = 1; REG Node = 'nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "2.046 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] } "NODE_NAME" } "" } } { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 3936 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.219 ns ( 10.70 % ) " "Info: Total cell delay = 0.219 ns ( 10.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.827 ns ( 89.30 % ) " "Info: Total interconnect delay = 1.827 ns ( 89.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "2.046 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.046 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] } { 0.000ns 1.827ns } { 0.000ns 0.219ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 source 2.346 ns - Longest register " "Info: - Longest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.346 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 2330 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 2330; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 765 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.635 ns) + CELL(0.711 ns) 2.346 ns nios_c6:inst\|sdram_0_s1_arbitrator:the_sdram_0_s1\|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1\|fifo_contains_ones_n 2 REG LC_X11_Y7_N4 15 " "Info: 2: + IC(1.635 ns) + CELL(0.711 ns) = 2.346 ns; Loc. = LC_X11_Y7_N4; Fanout = 15; REG Node = 'nios_c6:inst\|sdram_0_s1_arbitrator:the_sdram_0_s1\|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1\|fifo_contains_ones_n'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "2.346 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n } "NODE_NAME" } "" } } { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 2378 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.31 % ) " "Info: Total cell delay = 0.711 ns ( 30.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.635 ns ( 69.69 % ) " "Info: Total interconnect delay = 1.635 ns ( 69.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "2.346 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.346 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n } { 0.000ns 1.635ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "2.046 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.046 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] } { 0.000ns 1.827ns } { 0.000ns 0.219ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "2.346 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.346 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n } { 0.000ns 1.635ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 2378 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.452 ns - " "Info: - Micro setup delay of destination is 0.452 ns" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 3936 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "2.046 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.046 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] } { 0.000ns 1.827ns } { 0.000ns 0.219ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "2.346 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.346 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n } { 0.000ns 1.635ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.379 ns - Longest register register " "Info: - Longest register to register delay is 16.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns nios_c6:inst\|sdram_0_s1_arbitrator:the_sdram_0_s1\|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1\|fifo_contains_ones_n 1 REG LC_X11_Y7_N4 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y7_N4; Fanout = 15; REG Node = 'nios_c6:inst\|sdram_0_s1_arbitrator:the_sdram_0_s1\|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1\|fifo_contains_ones_n'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n } "NODE_NAME" } "" } } { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 2378 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.314 ns) + CELL(0.442 ns) 1.756 ns nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|cpu_0_instruction_master_qualified_request_flash_s1~185 2 COMB LC_X12_Y11_N7 1 " "Info: 2: + IC(1.314 ns) + CELL(0.442 ns) = 1.756 ns; Loc. = LC_X12_Y11_N7; Fanout = 1; COMB Node = 'nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|cpu_0_instruction_master_qualified_request_flash_s1~185'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "1.756 ns" { nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_flash_s1~185 } "NODE_NAME" } "" } } { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 3616 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.917 ns) + CELL(0.292 ns) 3.965 ns nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|cpu_0_instruction_master_qualified_request_flash_s1~186 3 COMB LC_X23_Y11_N8 14 " "Info: 3: + IC(1.917 ns) + CELL(0.292 ns) = 3.965 ns; Loc. = LC_X23_Y11_N8; Fanout = 14; COMB Node = 'nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|cpu_0_instruction_master_qualified_request_flash_s1~186'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "2.209 ns" { nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_flash_s1~185 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_flash_s1~186 } "NODE_NAME" } "" } } { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 3616 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.221 ns) + CELL(0.114 ns) 5.300 ns nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|lan91c111_s1_in_a_read_cycle~54 4 COMB LC_X21_Y11_N8 4 " "Info: 4: + IC(1.221 ns) + CELL(0.114 ns) = 5.300 ns; Loc. = LC_X21_Y11_N8; Fanout = 4; COMB Node = 'nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|lan91c111_s1_in_a_read_cycle~54'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "1.335 ns" { nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_flash_s1~186 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|lan91c111_s1_in_a_read_cycle~54 } "NODE_NAME" } "" } } { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 3725 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.417 ns) + CELL(0.432 ns) 6.149 ns nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|add~808COUT1_831 5 COMB LC_X21_Y11_N0 2 " "Info: 5: + IC(0.417 ns) + CELL(0.432 ns) = 6.149 ns; Loc. = LC_X21_Y11_N0; Fanout = 2; COMB Node = 'nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|add~808COUT1_831'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "0.849 ns" { nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|lan91c111_s1_in_a_read_cycle~54 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~808COUT1_831 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 6.757 ns nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|add~816 6 COMB LC_X21_Y11_N1 31 " "Info: 6: + IC(0.000 ns) + CELL(0.608 ns) = 6.757 ns; Loc. = LC_X21_Y11_N1; Fanout = 31; COMB Node = 'nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|add~816'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "0.608 ns" { nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~808COUT1_831 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~816 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.959 ns) + CELL(0.114 ns) 9.830 ns nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[7\]~105 7 COMB LC_X19_Y13_N8 12 " "Info: 7: + IC(2.959 ns) + CELL(0.114 ns) = 9.830 ns; Loc. = LC_X19_Y13_N8; Fanout = 12; COMB Node = 'nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[7\]~105'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "3.073 ns" { nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~816 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7]~105 } "NODE_NAME" } "" } } { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 3936 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.237 ns) + CELL(0.114 ns) 11.181 ns nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|outgoing_tri_state_bridge_0_data\[7\]~328 8 COMB LC_X20_Y11_N2 1 " "Info: 8: + IC(1.237 ns) + CELL(0.114 ns) = 11.181 ns; Loc. = LC_X20_Y11_N2; Fanout = 1; COMB Node = 'nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|outgoing_tri_state_bridge_0_data\[7\]~328'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "1.351 ns" { nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7]~105 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|outgoing_tri_state_bridge_0_data[7]~328 } "NODE_NAME" } "" } } { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 3737 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.590 ns) 12.216 ns nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[7\]~COMB_OUT 9 COMB LC_X20_Y11_N8 1 " "Info: 9: + IC(0.445 ns) + CELL(0.590 ns) = 12.216 ns; Loc. = LC_X20_Y11_N8; Fanout = 1; COMB Node = 'nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[7\]~COMB_OUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "1.035 ns" { nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|outgoing_tri_state_bridge_0_data[7]~328 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7]~COMB_OUT } "NODE_NAME" } "" } } { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 3936 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.963 ns) + CELL(0.200 ns) 16.379 ns nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[7\] 10 REG IOC_X8_Y21_N1 1 " "Info: 10: + IC(3.963 ns) + CELL(0.200 ns) = 16.379 ns; Loc. = IOC_X8_Y21_N1; Fanout = 1; REG Node = 'nios_c6:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "4.163 ns" { nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7]~COMB_OUT nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] } "NODE_NAME" } "" } } { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 3936 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.906 ns ( 17.74 % ) " "Info: Total cell delay = 2.906 ns ( 17.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.473 ns ( 82.26 % ) " "Info: Total interconnect delay = 13.473 ns ( 82.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "16.379 ns" { nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_flash_s1~185 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_flash_s1~186 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|lan91c111_s1_in_a_read_cycle~54 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~808COUT1_831 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~816 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7]~105 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|outgoing_tri_state_bridge_0_data[7]~328 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7]~COMB_OUT nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "16.379 ns" { nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_flash_s1~185 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_flash_s1~186 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|lan91c111_s1_in_a_read_cycle~54 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~808COUT1_831 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~816 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7]~105 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|outgoing_tri_state_bridge_0_data[7]~328 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7]~COMB_OUT nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] } { 0.000ns 1.314ns 1.917ns 1.221ns 0.417ns 0.000ns 2.959ns 1.237ns 0.445ns 3.963ns } { 0.000ns 0.442ns 0.292ns 0.114ns 0.432ns 0.608ns 0.114ns 0.114ns 0.590ns 0.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "2.046 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.046 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] } { 0.000ns 1.827ns } { 0.000ns 0.219ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "2.346 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.346 ns" { altpll0:inst1|altpll:altpll_component|_clk0 nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n } { 0.000ns 1.635ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "16.379 ns" { nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_flash_s1~185 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_flash_s1~186 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|lan91c111_s1_in_a_read_cycle~54 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~808COUT1_831 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~816 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7]~105 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|outgoing_tri_state_bridge_0_data[7]~328 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7]~COMB_OUT nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "16.379 ns" { nios_c6:inst|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module:rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1|fifo_contains_ones_n nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_flash_s1~185 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_flash_s1~186 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|lan91c111_s1_in_a_read_cycle~54 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~808COUT1_831 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~816 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7]~105 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|outgoing_tri_state_bridge_0_data[7]~328 nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7]~COMB_OUT nios_c6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7] } { 0.000ns 1.314ns 1.917ns 1.221ns 0.417ns 0.000ns 2.959ns 1.237ns 0.445ns 3.963ns } { 0.000ns 0.442ns 0.292ns 0.114ns 0.432ns 0.608ns 0.114ns 0.114ns 0.590ns 0.200ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "altpll0:inst1\|altpll:altpll_component\|_clk1 " "Info: No valid register-to-register data paths exist for clock \"altpll0:inst1\|altpll:altpll_component\|_clk1\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}