📄 nios_c6.ptf.bak
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width = "16";
Is_Enabled = "1";
}
PORT zs_dqm
{
direction = "output";
width = "2";
Is_Enabled = "1";
}
PORT zs_ras_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_we_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT az_addr
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "22";
}
PORT az_be_n
{
Is_Enabled = "1";
direction = "input";
type = "byteenable_n";
width = "2";
}
PORT az_cs
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT az_data
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "16";
}
PORT az_rd_n
{
Is_Enabled = "1";
direction = "input";
type = "read_n";
width = "1";
}
PORT az_wr_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT za_data
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "16";
}
PORT za_valid
{
Is_Enabled = "1";
direction = "output";
type = "readdatavalid";
width = "1";
}
PORT za_waitrequest
{
Is_Enabled = "1";
direction = "output";
type = "waitrequest";
width = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "sdram";
Disable_Simulation_Port_Wiring = "0";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = "4194304 x 16<br>
Memory size: 8 MBytes<br>
64 MBits
";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
register_data_in = "1";
sim_model_base = "1";
sdram_data_width = "16";
sdram_addr_width = "12";
sdram_row_width = "12";
sdram_col_width = "8";
sdram_num_chipselects = "1";
sdram_num_banks = "4";
refresh_period = "15.625";
powerup_delay = "100";
cas_latency = "3";
t_rfc = "70";
t_rp = "20";
t_mrd = "3";
t_rcd = "20";
t_ac = "5.5";
t_wr = "14";
init_refresh_commands = "2";
init_nop_delay = "0";
shared_data = "0";
starvation_indicator = "0";
tristate_bridge_slave = "";
is_initialized = "1";
sdram_bank_width = "2";
MAKE
{
TARGET delete_placeholder_warning
{
sdram_0
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET sim
{
sdram_0
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
}
SIMULATION
{
Fix_Me_Up = "";
DISPLAY
{
SIGNAL a
{
name = "az_addr";
radix = "hexadecimal";
}
SIGNAL b
{
name = "az_be_n";
radix = "hexadecimal";
}
SIGNAL c
{
name = "az_cs";
}
SIGNAL d
{
name = "az_data";
radix = "hexadecimal";
}
SIGNAL e
{
name = "az_rd_n";
}
SIGNAL f
{
name = "az_wr_n";
}
SIGNAL g
{
name = "clk";
}
SIGNAL h
{
name = "za_data";
radix = "hexadecimal";
}
SIGNAL i
{
name = "za_valid";
}
SIGNAL j
{
name = "za_waitrequest";
}
SIGNAL k
{
name = "za_cannotrefresh";
suppress = "1";
}
SIGNAL l
{
name = "CODE";
radix = "ascii";
}
SIGNAL m
{
name = "zs_addr";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL n
{
name = "zs_ba";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL o
{
name = "zs_cs_n";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL p
{
name = "zs_ras_n";
suppress = "0";
}
SIGNAL q
{
name = "zs_cas_n";
suppress = "0";
}
SIGNAL r
{
name = "zs_we_n";
suppress = "0";
}
SIGNAL s
{
name = "zs_dq";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL t
{
name = "zs_dqm";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL u
{
name = "zt_addr";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL v
{
name = "zt_ba";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL w
{
name = "zt_oe";
suppress = "1";
}
SIGNAL x
{
name = "zt_cke";
suppress = "1";
}
SIGNAL y
{
name = "zt_chipselect";
suppress = "1";
}
SIGNAL z0
{
name = "zt_lock_n";
suppress = "1";
}
SIGNAL z1
{
name = "zt_ras_n";
suppress = "1";
}
SIGNAL z2
{
name = "zt_cas_n";
suppress = "1";
}
SIGNAL z3
{
name = "zt_we_n";
suppress = "1";
}
SIGNAL z4
{
name = "zt_cs_n";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z5
{
name = "zt_dqm";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z6
{
name = "zt_data";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z7
{
name = "tz_data";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z8
{
name = "tz_waitrequest";
suppress = "1";
}
}
PORT_WIRING
{
PORT clk
{
Is_Enabled = "1";
direction = "input";
width = "1";
}
PORT zs_addr
{
Is_Enabled = "1";
direction = "input";
width = "12";
}
PORT zs_ba
{
Is_Enabled = "1";
direction = "input";
width = "2";
}
PORT zs_cas_n
{
Is_Enabled = "1";
direction = "input";
width = "1";
}
PORT zs_cke
{
Is_Enabled = "1";
direction = "input";
width = "1";
}
PORT zs_cs_n
{
Is_Enabled = "1";
direction = "input";
width = "1";
}
PORT zs_dq
{
Is_Enabled = "1";
direction = "inout";
width = "16";
}
PORT zs_dqm
{
Is_Enabled = "1";
direction = "input";
width = "2";
}
PORT zs_ras_n
{
Is_Enabled = "1";
direction = "input";
width = "1";
}
PORT zs_we_n
{
Is_Enabled = "1";
direction = "input";
width = "1";
}
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram_0.v, __PROJECT_DIRECTORY__/sdram_0_test_component.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE led_pio
{
class = "altera_avalon_pio";
class_version = "5.11";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/led_pio.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "2";
}
PORT out_port
{
direction = "output";
Is_Enabled = "1";
width = "2";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
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