📄 nios_c6.ptf.bak
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Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8 <br>Read Depth: 64; Read IRQ Threshold: 8";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
write_depth = "64";
read_depth = "64";
write_threshold = "8";
read_threshold = "8";
read_char_stream = "";
showascii = "1";
read_le = "0";
write_le = "0";
altera_show_unreleased_jtag_uart_features = "0";
}
SIMULATION
{
Fix_Me_Up = "";
DISPLAY
{
SIGNAL av_chipselect
{
name = "av_chipselect";
}
SIGNAL av_address
{
name = "av_address";
radix = "hexadecimal";
}
SIGNAL av_read_n
{
name = "av_read_n";
}
SIGNAL av_readdata
{
name = "av_readdata";
radix = "hexadecimal";
}
SIGNAL av_write_n
{
name = "av_write_n";
}
SIGNAL av_writedata
{
name = "av_writedata";
radix = "hexadecimal";
}
SIGNAL av_waitrequest
{
name = "av_waitrequest";
}
SIGNAL av_irq
{
name = "av_irq";
}
SIGNAL dataavailable
{
name = "dataavailable";
}
SIGNAL readyfordata
{
name = "readyfordata";
}
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "nios2-terminal";
}
INTERACTIVE_OUT log
{
enable = "1";
exe = "perl -- atail-f.pl";
file = "_output_stream.dat";
radix = "ascii";
signals = "temp,list";
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart_0.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE flash
{
class = "altera_avalon_cfi_flash";
class_version = "5.11";
iss_model_name = "altera_avalon_flash";
HDL_INFO
{
}
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "8";
is_shared = "1";
direction = "inout";
type = "data";
}
PORT address
{
width = "21";
is_shared = "1";
direction = "input";
type = "address";
}
PORT read_n
{
width = "1";
is_shared = "1";
direction = "input";
type = "read_n";
}
PORT write_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "write_n";
}
PORT select_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
class = "altera_avalon_cfi_flash";
Supports_Flash_File_System = "1";
flash_reference_designator = "U6";
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Nonvolatile_Storage = "1";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Base_Address = "0x00000000";
Data_Width = "8";
Address_Width = "21";
Simulation_Num_Lanes = "1";
Convert_Xs_To_0 = "1";
Write_Wait_States = "160ns";
Read_Wait_States = "160ns";
Setup_Time = "60ns";
Hold_Time = "60ns";
Address_Span = "2097152";
MASTERED_BY tri_state_bridge_0/tristate_master
{
priority = "1";
}
Address_Group = "0";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "1";
}
}
SYSTEM_BUILDER_INFO
{
Make_Memory_Model = "1";
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Setup_Value = "60";
Wait_Value = "160";
Hold_Value = "60";
Timing_Units = "ns";
Unit_Multiplier = "1";
Size = "2097152";
MAKE
{
MACRO
{
FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(FLASH_FLASHTARGET_TMP1:0=)";
FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
}
MASTER cpu_0
{
MACRO
{
BOOT_COPIER = "boot_loader_cfi.srec";
CPU_CLASS = "altera_nios2";
CPU_RESET_ADDRESS = "0x0";
}
}
TARGET delete_placeholder_warning
{
flash
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET flashfiles
{
flash
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2flash --input=$(ELF) --flash=U6 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER) --outfile=$(FLASH_FLASHTARGET_ALT_SIM_PREFIX)flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x1FFFFF --reset=$(CPU_RESET_ADDRESS) ";
Dependency = "$(ELF)";
Target_File = "$(FLASH_FLASHTARGET_ALT_SIM_PREFIX)flash.flash";
}
}
TARGET sim
{
flash
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
}
}
MODULE lan91c111
{
class = "altera_avalon_lan91c111";
class_version = "5.1";
WIZARD_SCRIPT_ARGUMENTS
{
Is_Ethernet_Mac = "1";
CONSTANTS
{
CONSTANT LAN91C111_REGISTERS_OFFSET
{
value = "0x0300";
comment = "offset 0 or 0x300, depending on address bus wiring";
}
CONSTANT LAN91C111_DATA_BUS_WIDTH
{
value = "32";
comment = "width 16 or 32, depending on data bus wiring";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "0";
Wire_Test_Bench_Values = "1";
Is_Enabled = "1";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
}
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "0";
Is_Enabled = "1";
Is_Bus_Master = "0";
Bus_Type = "avalon_tristate";
Uses_Tri_State_Data_Bus = "1";
Address_Alignment = "native";
Address_Width = "14";
Data_Width = "32";
Has_IRQ = "1";
Read_Wait_States = "175ns";
Write_Wait_States = "175ns";
Setup_Time = "10ns";
Hold_Time = "5ns";
Is_Memory_Device = "0";
Date_Modified = "2002.03.19.10:51:51";
Base_Address = "0x00200000";
Tri_State_Data_Bus = "--unknown--";
MASTERED_BY tri_state_bridge_0/tristate_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "1";
}
Address_Group = "0";
}
PORT_WIRING
{
PORT irq
{
direction = "output";
width = "1";
type = "irq";
test_bench_value = "0";
}
PORT byteenablen
{
is_shared = "1";
direction = "input";
width = "4";
type = "byteenable_n";
}
PORT address
{
is_shared = "1";
direction = "input";
width = "14";
type = "address";
}
PORT data
{
is_shared = "1";
direction = "inout";
width = "32";
type = "data";
}
PORT iow_n
{
direction = "input";
width = "1";
type = "write_n";
}
PORT ior_n
{
direction = "input";
width = "1";
type = "read_n";
}
PORT reset
{
direction = "input";
width = "1";
type = "reset";
}
PORT reset_n
{
direction = "input";
width = "1";
type = "reset_n";
Is_Enabled = "0";
}
PORT ardy
{
direction = "output";
width = "1";
type = "inhibitrequest_n";
Is_Enabled = "0";
}
}
}
}
MODULE sdram_0
{
class = "altera_avalon_new_sdram_controller";
class_version = "5.11";
iss_model_name = "altera_memory";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Maximum_Pending_Read_Transactions = "7";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Is_Memory_Device = "1";
Address_Width = "22";
Data_Width = "16";
Simulation_Num_Lanes = "1";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Base_Address = "0x00800000";
Address_Group = "0";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
PORT_WIRING
{
PORT zs_addr
{
direction = "output";
width = "12";
Is_Enabled = "1";
}
PORT zs_ba
{
direction = "output";
width = "2";
Is_Enabled = "1";
}
PORT zs_cas_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_cke
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_cs_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_dq
{
direction = "inout";
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