logic.v

SRAM和USB芯片FT245的VERILOG逻辑控制

integer Spointer;
reg [7:0]SframeBuf[15:0];	//16 BYTES

always @(posedge div4_clk)//div4_clk=5M
	if ((reset) && (USBTXE == 0) && (SendEN == 1) && (USBRXF == 1)) //SendEN为发送允许信号，发送数据的逻辑电路置位
  		begin
    		case(Sstate)
     			3'b000:
        			begin
						reg_USB_WR <= 1;      //产生写信号的上升沿
          				Sstate <= 3'b001;
						sram_rd_clk <= 0;
        			end
     			3'b001:
					begin
						reg_USB_DATA[7:0] <= S_IO[15:8];//SframeBuf[Spointer]; //写高字节到FIFO
						Sstate <= 3'b010;
            		end
     			3'b010:
        			begin
						reg_USB_WR <= 0;         //产生写usb WR FIFO信号的下降沿
            			Sstate <= 3'b011;
         			end	
				3'b011:
        			begin
						reg_USB_WR <= 1;      //产生写信号的上升沿
          				Sstate <= 3'b100;
        			end
     			3'b100:
					begin
						reg_USB_DATA[7:0] <= S_IO[7:0];//SframeBuf[Spointer]; //写低字节到FIFO
						Sstate <= 3'b101;
            		end
     			3'b101:
        			begin
						reg_USB_WR <= 0;         //产生写usb WR FIFO信号的下降沿
            			Sstate <= 3'b000;
						sram_rd_clk <= 1;
         			end	
				default:
					begin
						Sstate <= 3'b000;
						reg_USB_WR <= 0;
						sram_rd_clk <= 0;
					end
			endcase
  		end
	else
  		begin
    		reg_USB_WR <= 0;
			reg_USB_DATA <= 0;
  		end
assign USBWR = reg_USB_WR;
assign USBD = ((SendEN == 1) && (USBRXF == 1)) ? reg_USB_DATA : 8'bzzzzzzzz;
/**************************DSP to FPGA*****COMMAND*********************/
reg reg_COMMAND_DSP;
//assign _CSDB = 1'b0;
//assign _DBDIR = (read_SRAM_en == 1) ?  1'b0 : 1'b1;
//
always @(posedge div4_clk)
	if ((read_SRAM_en == 1) && (RD_empty_flag == 0))
		begin
			SendEN <= 1;
			read_sram_CLK <= sram_rd_clk;
		end
	else 
		begin
			SendEN <= 0;
			read_sram_CLK <= 1;
		end
		
//
assign LED1 = (read_SRAM_en == 1) ? 1'b0 : 1'b1;
assign LED2 = (sample_to_SRAM_en == 1) ? 1'b0 : 1'b1;
////////////////////////////////////////////////////
/*DSP接口
input [7:0]BA;
inout [15:0]BD;
output _RDYIO,_DBDIR,_CSDB;
input PAGE2IO,R_WIO,XF1,XF0;	
*/
reg reg_XF0,reg_XF1,reg_PAGE2IO;
reg [15:0]wr_reg_BD,rd_reg_BD;
always @(posedge CLK_40M)
	reg_XF0 <= XF0;
always @(posedge CLK_40M)
	reg_XF1 <= XF1;	
always @(posedge CLK_40M)
	reg_PAGE2IO <= PAGE2IO;	
assign _CSDB = (reg_XF0 == 1) ?  1'b0 : 1'b1;
assign _DBDIR = (reg_XF0 == 1) ?  1'b0 : 1'b1;
assign BD = (reg_XF0 == 0) ? rd_reg_BD : 16'bzzzzzzzzzzzzzzzz;

always @(negedge reg_XF1)
	if ((reg_XF0 == 1) && (PAGE2IO == 0))
		wr_reg_BD <= BD;
always @(posedge reg_XF1)
	if ((reg_XF0 == 0) && (PAGE2IO == 0))
		rd_reg_BD <= wr_reg_BD + 1;
//assign LED1 = (reg_XF0 == 1) ? 1'b0 : 1'b1;
//assign LED2 = (reg_XF0 == 0) ? 1'b0 : 1'b1;
//////////////////////////////////////////////////////////
endmodule