logic.v

SRAM和USB芯片FT245的VERILOG逻辑控制

	else if (read_SRAM_en == 1)
		reg_addr_wr <= 0;
always @(posedge reg_DRY or negedge reset)
	if (~reset)
		WR_full_flag <= 0;
	else if (reg_addr_wr == 21'b111111111111111111111)
		WR_full_flag <= 1;
	else
		WR_full_flag <= 0;
assign S_CE1 = (sample_to_SRAM_en == 1) ? reg_addr_wr[20] : RD_S_CE1;
assign S_CE2 = (sample_to_SRAM_en == 1) ? ~reg_addr_wr[20] : RD_S_CE2;
assign S_WE = ((start_WRsram == 1) && (WR_full_flag == 0)) ? reg_DRY : 1'b1;
assign S_A[19:0] = (sample_to_SRAM_en == 1) ? reg_addr_wr[19:0] : reg_addr_rd[19:0];	
/**************************sram to dsp*****read sram*************************/
reg RD_empty_flag;
always @(posedge read_sram_CLK or negedge reset)	//SRAM读地址控制
	if (~reset)
		reg_addr_rd <= 0;
	else if ((read_SRAM_en == 1) && (reg_addr_rd < 21'b111111111111111111111))
		reg_addr_rd <= reg_addr_rd + 1'b1;
	else if (sample_to_SRAM_en == 1)
		reg_addr_rd <= 0;
always @(posedge read_sram_CLK or negedge reset)
	if (~reset)
		RD_empty_flag <= 0;
	else if (reg_addr_rd == 21'b111111111111111111111)
		RD_empty_flag <= 1;
	else
		RD_empty_flag <= 0;	
assign RD_S_CE1 = (read_SRAM_en == 1) ? reg_addr_rd[20] : 1'b1;
assign RD_S_CE2 = (read_SRAM_en == 1) ? ~reg_addr_rd[20] : 1'b1;
assign S_OE = ((read_SRAM_en == 1) &&(RD_empty_flag ==0)) ? 1'b0 : 1'b1;
assign BD = (read_SRAM_en == 1) ? S_IO : 16'bzzzzzzzzzzzzzzzz;	//DSP数据口和SRAM数据口相连
/***************************USB****connect to PC OR ARM9***************************/
//接收
reg reg_USB_RD;
reg [1:0]Rstate;
parameter FrameLen = 3;
integer Rpointer;
//reg [7:0]RframeBuf[2:0];	//3 BYTES[起始，数据，校验和]
reg [7:0]RframeBuf;
always @(posedge div4_clk)//div4_clk=5M
	if (USBRXF == 0)
		begin
       		case(Rstate)
				2'b00:
 					begin
						reg_USB_RD <= 1'b0;	//产生读信号的下降沿
         				Rstate <= 2'b01;
        			end
        		2'b01:
					begin
						RframeBuf <= USBD; //读FT245BM芯片FIFO的当前字节
						Rstate <= 2'b10;
					end
				2'b10:
         			begin
						reg_USB_RD <= 1'b1;
						Rstate <= 2'b00;
          			end
				default:
					begin
						reg_USB_RD <= 1'b1;
						Rstate <= 2'b00;
          			end
			endcase
		end
	else
		begin
       		reg_USB_RD <= 1;
     	end
always @(posedge div4_clk)//div4_clk=5M
	if (RframeBuf == 1)//读
		begin
			read_SRAM_en <= 1;
			sample_to_SRAM_en <= 0;
			reset <= 1'b1;
		end
	else if (RframeBuf == 2)//采
		begin
			read_SRAM_en <= 0;
			sample_to_SRAM_en <= 1;
			reset <= 1'b1;
		end
	else if (RframeBuf == 3)//reset
		begin
			reset <= 1'b0;
			read_SRAM_en <= 0;
			sample_to_SRAM_en <= 0;
		end
	else
		begin
			read_SRAM_en <= 0;
			sample_to_SRAM_en <= 0;
			reset <= 1'b1;
		end 
assign USBRD = reg_USB_RD;
//发送
reg reg_USB_WR;
reg SendEN,sram_rd_clk;
reg [2:0]Sstate;
reg [7:0]reg_USB_DATA;
parameter FrameLen_S = 16;