⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 新建 文本文档.txt

📁 fir滤波器 实现低通 模拟和数字转换
💻 TXT
字号:
package eight_bit_int is --user defined types
subtype byte is integer range -128 to 127;
type array_byte is array(0 to 3)of byte;
end eight_bit_int;
library work;
use work.eight_bit_int.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity fir_srg is   ----->interface
port (clk : in  std_logic;
  x : in  byte;
  y : out byte);
end fir_srg;
architecture flex of fir_srg is
signal tap :array_byte; --tapped delay line of bytes
begin 
p1:process   ----->behavioral style
begin 
wait until clk='1';
--compute output y with the filter coefficients weight.
--the coefficients are [-1 3.75 3.75 -1].
--multiplication and division for altera vhdl are only
--allowed for powers of two!
y<=2*tap(1)+tap(1)+tap(1)/2+tap(1)/4
   +2*tap(2)+tap(2)+tap(2)/2+tap(2)/4
   -tap(3)-tap(0);
for i in 3 downto 1 loop
tap(i)<=tap(i-1);--tapped delay line:shift one
end loop;
tap(0)<=x;
end process;
end flex;



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity fir_filter is
generic(k:integer:=4;n:integer:=8);
port(rst:in std_logic;
clk:in std_logic;
xn_in  : in signed(n-1 downto 0);
yn_out : out signed(2*n-1 downto 0));
end fir_filter;
architecture behavioral of fir_filter is
constant m:integer:=4;------------------------circuit has four stages
type regists is array(k-2 downto 0)of signed(n-1 downto 0);
type cofficients is array(k-1 downto 0)of signed(n-1 downto 0);
signal tmp:regists;
constant coef:cofficients:=("00001010","01001011","10010100","00111001");

begin 
process (clk,rst)
variable acc,prod:signed(2*n-1 downto 0):=(others=>'0');
variable mark :std_logic;
begin 
  if (rst='1')then
   for  i in k-2 downto 0 loop
    for j in n-1 downto 0 loop
     tmp(i)(j)<='0';
    end loop;
   end loop;
  elsif(clk'event and clk='1')then
   acc:=coef(0)*xn_in;
   for i in 1 to k-1 loop
    mark:=acc(2*n-1);
    prod:=coef(i)*tmp(k-1-i);
    acc:=acc+prod;
    if(mark=prod(prod'left))and(acc(acc'left)/=mark)then
     acc:=(15=>mark,others=>not mark);
    end if;
   end loop;
   tmp<=xn_in&tmp(k-2 downto 1);
  end if;
  yn_out<=acc;
end process;
end behavioral;

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -