📄 systema.mdl
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Ports [1]
Position [750, 219, 780, 251]
Floating off
Location [686, 299, 1019, 484]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "4"
YMin "-1"
YMax "1"
SaveName "ScopeData1"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Block {
BlockType Scope
Name "nroll"
Ports [1]
Position [750, 149, 780, 181]
Floating off
Location [5, 52, 1021, 729]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "0.25"
YMin "-1"
YMax "1"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Block {
BlockType Scope
Name "nyaw"
Ports [1]
Position [750, 289, 780, 321]
Floating off
Location [686, 544, 1019, 734]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "5 "
YMin "0"
YMax "0.22"
SaveName "ScopeData2"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Block {
BlockType Scope
Name "x"
Ports [1]
Position [535, 429, 565, 461]
Floating off
Location [6, 424, 339, 732]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "5 "
YMin "0"
YMax "0.009"
SaveName "ScopeData4"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Block {
BlockType Scope
Name "y"
Ports [1]
Position [535, 499, 565, 531]
Floating off
Location [6, 424, 339, 732]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "5 "
YMin "0"
YMax "0.009"
SaveName "ScopeData6"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Block {
BlockType Scope
Name "zd"
Ports [1]
Position [460, 394, 490, 426]
Floating off
Location [5, 52, 1021, 729]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "10 "
YMin "-110.5"
YMax "-107.25"
SaveName "ScopeData18"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Line {
SrcBlock "Demux"
SrcPort 1
DstBlock "nroll"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 4
DstBlock "ndpitch"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 8
DstBlock "zd"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 7
DstBlock "fz"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 6
DstBlock "ndyaw"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 2
DstBlock "ndroll"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 5
DstBlock "nyaw"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 3
DstBlock "npitch"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Demux"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 9
DstBlock "x"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 10
DstBlock "dx"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 11
DstBlock "y"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 12
DstBlock "dy"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "W. NORMAL NOISE"
Ports [1, 1]
Position [435, 239, 475, 271]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "W. NORMAL NOISE"
Location [1016, 88, 1843, 514]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [250, 308, 280, 322]
IconDisplay "Port number"
}
Block {
BlockType Demux
Name "Demux"
Ports [1, 12]
Position [370, 34, 380, 591]
BackgroundColor "black"
ShowName off
Outputs "12"
}
Block {
BlockType Mux
Name "Mux2"
Ports [12, 1]
Position [770, 34, 780, 591]
ShowName off
Inputs "12"
DisplayOption "bar"
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [470, 30, 490, 50]
ShowName off
IconShape "round"
Inputs "|++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum2"
Ports [2, 1]
Position [475, 75, 495, 95]
ShowName off
IconShape "round"
Inputs "|++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum4"
Ports [2, 1]
Position [470, 120, 490, 140]
ShowName off
IconShape "round"
Inputs "|++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum5"
Ports [2, 1]
Position [465, 165, 485, 185]
ShowName off
IconShape "round"
Inputs "|++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum6"
Ports [2, 1]
Position [470, 210, 490, 230]
ShowName off
IconShape "round"
Inputs "|++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum7"
Ports [2, 1]
Position [465, 255, 485, 275]
ShowName off
IconShape "round"
Inputs "|++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum8"
Ports [2, 1]
Position [465, 300, 485, 320]
ShowName off
IconShape "round"
Inputs "|++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Reference
Name "dot pitchw noise"
Ports [0, 1]
Position [420, 167, 435, 183]
SourceBlock "simulink/Sources/Band-Limited\nWhite No"
"ise"
SourceType "Band-Limited White Noise."
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Cov "[0.0001]"
Ts "0.01"
seed "[23341]"
VectorParams1D on
}
Block {
BlockType Reference
Name "dot roll w noise"
Ports [0, 1]
Position [430, 77, 445, 93]
SourceBlock "simulink/Sources/Band-Limited\nWhite No"
"ise"
SourceType "Band-Limited White Noise."
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Cov "[0.0001]"
Ts "0.01"
seed "[23341]"
VectorParams1D on
}
Block {
BlockType Reference
Name "dot yaw w noise"
Ports [0, 1]
Position [420, 257, 435, 273]
SourceBlock "simulink/Sources/Band-Limited\nWhite No"
"ise"
SourceType "Band-Limited White Noise."
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Cov "[0.0001]"
Ts "0.01"
seed "[23341]"
VectorParams1D on
}
Block {
BlockType Reference
Name "pitch w noise"
Ports [0, 1]
Position [425, 122, 440, 138]
SourceBlock "simulink/Sources/Band-Limited\nWhite No"
"ise"
SourceType "Band-Limited White Noise."
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Cov "[0.00001]"
Ts "0.01"
seed "[23341]"
VectorParams1D on
}
Block {
BlockType Reference
Name "roll w noise"
Ports [0, 1]
Position [425, 32, 440, 48]
SourceBlock "simulink/Sources/Band-Limited\nWhite No"
"ise"
SourceType "Band-Limited White Noise."
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Cov "[0.00001]"
Ts "0.01"
seed "[24431]"
VectorParams1D on
}
Block {
BlockType Reference
Name "yaw w noise"
Ports [0, 1]
Position [425, 212, 440, 228]
SourceBlock "simulink/Sources/Band-Limited\nWhite No"
"ise"
SourceType "Band-Limited White Noise."
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Cov "[0.00001]"
Ts "0.01"
seed "[23341]"
VectorParams1D on
}
Block {
BlockType Reference
Name "z w noise"
Ports [0, 1]
Position [420, 302, 435, 318]
SourceBlock "simulink/Sources/Band-Limited\nWhite No"
"ise"
SourceType "Band-Limited White Noise."
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Cov "[0.00001]"
Ts "0.01"
seed "[23341]"
VectorParams1D on
}
Block {
BlockType Outport
Name "Out1"
Position [930, 308, 960, 322]
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