s3c2400.h.svn-base

vivi源代码

#define UCON_TM_DISABLE		0x0 
#define UCON_TM_INT		0x4 
#define UCON_TM_DMA0		0x8
#define UCON_TM_DMA1		0xC
#define UCON_RM_DISABLE		0x0
#define UCON_RM_INT		0x1
#define UCON_RM_DMA0		0x2
#define UCON_RM_DMA1		0x3

#define UFCON_TX_TRG_EMPTY	0x00
#define UFCON_TX_TRG_4BYTE	0x40
#define UFCON_TX_TRG_8BYTE	0x80
#define UFCON_TX_TRG_12BYTE	0xC0
#define UFCON_RX_TRG_4BYTE	0x00
#define UFCON_RX_TRG_8BYTE	0x10
#define UFCON_RX_TRG_12BYTE	0x20
#define UFCON_RX_TRG_16BYTE	0x30
#define UFCON_FIFO_EN		0x1

#define UNCON_AFC_EN		(1 << 4)
#define UFCON_RQT_SEND		0x1

#define UTRSTAT_TX_EMPTY	(1 << 2)
#define UTRSTAT_TX_BUF_EMPTY	(1 << 1)
#define UTRSTAT_RX_READY	(1 << 0)
#define S3C2400_UTRSTAT_ERROR_MASK	0xF
#endif

#if 0
#define UART0BASE	0x15000000	/* UART channel 0 */
#define UART1BASE	0x15004000	/* UART channel 1 */
#define bUART(Nb,x)     (0x15000000 + (Nb)*0x4000 + (x))
#endif
#define ULCON0          bUART(0,0x00)
#define UCON0           bUART(0,0x04)
#define UFCON0          bUART(0,0x08)
#define UMCON0          bUART(0,0x0c)
#define UTRSTAT0        bUART(0,0x10)
#define UERSTAT0        bUART(0,0x14)
#define UFSTAT0         bUART(0,0x18)
#define UMSTAT0         bUART(0,0x1c)
#define UTXH0           bUARTb(0,0x20)
#define URXH0           bUARTb(0,0x24)
#define UBRDIV0         bUART(0,0x28)
#define ULCON1          bUART(1,0x00)
#define UCON1           bUART(1,0x04)
#define UFCON1          bUART(1,0x08)
#define UMCON1          bUART(1,0x0c)
#define UTRSTAT1        bUART(1,0x10)
#define UERSTAT1        bUART(1,0x14)
#define UFSTAT1         bUART(1,0x18)
#define UMSTAT1         bUART(1,0x1c)
#define UTXH1           bUARTb(1,0x20)
#define URXH1           bUARTb(1,0x24)
#define UBRDIV1         bUART(1,0x28)
/* Status */
#if 0
#define UTRSTAT_TX_EMPTY	(1 << 2)
#define UTRSTAT_TX_BUF_EMPTY	(1 << 1)
#define UTRSTAT_RX_READY	(1 << 0)
#define S3C2400_UTRSTAT_ERROR_MASK	0xF
#endif
#define UTRSTAT_TX_EMPTY	(1 << 2)
#define UTRSTAT_RX_READY	(1 << 0)
#define UART_ERROR_MASK		0xF

/*
 * Interrupt Controller
 */
#define S3C2400_INT_CFG_BASE	0x14400000
#define bINT(Nb)	__REG(S3C2400_INT_CFG_BASE + (Nb))
#define S3C2400_SRCPND		0x00	/* R/W, Indicates the interrupt request status */
#define S3C2400_INTMOD		0x04	/* W, Intterupt mode reg. 0=IRQ, 1=FIQ */	
#define S3C2400_INTMSK		0x08	/* R/W, Intterupt mask */
#define S3C2400_PRIORITY	0x0C	/* W, IRQ priority control reg. */
#define S3C2400_INTPND		0x10	/* R/W, Indicates the irq rqt status */
#define S3C2400_INTOFFSET	0x14	/* R,  */

#define _SRCPND		bINT(0x00)	/* R/W, Indicates the interrupt request status */
#define _INTMOD		bINT(0x04)	/* W, Intterupt mode reg. 0=IRQ, 1=FIQ */	
#define _INTMSK		bINT(0x08)	/* R/W, Intterupt mask */
#define _PRIORITY	bINT(0x0C)	/* W, IRQ priority control reg. */
#define _INTPND		bINT(0x10)	/* R/W, Indicates the irq rqt status */
#define _INTOFFSET	bINT(0x14)	/* R,  */

#define IRQ_ADC		(1 << 31) /* ADC EOC interrupt        */
#define IRQ_RTC		(1 << 30) /* RTC alarm interrupt      */
#define IRQ_UTXD1	(1 << 29) /* UART1 transmit interrupt */
#define IRQ_UTXD0	(1 << 28) /* UART0 transmit interrupt */
#define IRQ_IIC		(1 << 27) /* IIC interrupt        */
#define IRQ_USBH	(1 << 26) /* USB host interrupt       */
#define IRQ_USBD	(1 << 25) /* USB device interrupt     */
#define IRQ_URXD1	(1 << 24) /* UART1 receive interrupt  */
#define IRQ_URXD0	(1 << 23) /* UART0 receive interrupt  */
#define IRQ_SPI		(1 << 22) /* SPI interrupt        */
#define IRQ_MMC		(1 << 21) /* MMC interrupt        */
#define IRQ_DMA3	(1 << 20) /* DMA channel 3 interrupt  */
#define IRQ_DMA2	(1 << 19) /* DMA channel 2 interrupt  */
#define IRQ_DMA1	(1 << 18) /* DMA channel 1 interrupt  */
#define IRQ_DMA0	(1 << 17) /* DMA channel 0 interrupt  */
#define IRQ_RESERVED	(1 << 16) /* reserved for future use  */
#define IRQ_UERR01	(1 << 15) /* UART 0/1 interrupt       */
#define IRQ_TIMER4	(1 << 14) /* Timer 4 interrupt        */
#define IRQ_TIMER3	(1 << 13) /* Timer 3 interrupt        */
#define IRQ_TIMER2	(1 << 12) /* Timer 2 interrupt        */
#define IRQ_TIMER1	(1 << 11) /* Timer 1 interrupt        */
#define IRQ_TIMER0	(1 << 10) /* Timer 0 interrupt        */
#define IRQ_WDT		(1 <<  9) /* Watch-Dog timer interrupt    */
#define IRQ_TICK	(1 <<  8) /* RTC time tick interrupt  */
#define IRQ_EINT7	(1 <<  7) /* External interrupt 7     */
#define IRQ_EINT6	(1 <<  6) /* External interrupt 6     */
#define IRQ_EINT5	(1 <<  5) /* External interrupt 5     */
#define IRQ_EINT4	(1 <<  4) /* External interrupt 4     */
#define IRQ_EINT3	(1 <<  3) /* External interrupt 3     */
#define IRQ_EINT2	(1 <<  2) /* External interrupt 2     */
#define IRQ_EINT1	(1 <<  1) /* External interrupt 1     */
#define IRQ_EINT0	(1 <<  0) /* External interrupt 0     */
/*
 * Watch-dog timer
 */
#define S3C2400_WTCON		0x15300000	/* R/W, Watch-dog timer control reg. */
#define S3C2400_WTDAT		0x15300004	/* R/W, Watch-dog timer data reg. */
#define S3C2400_WTCNT		0x15300008	/* R/W, Watch-dog tiemr count value for reload */

/*
 * I/O Ports
 */
#define S3C2400_IOPORT_BASE_ADDR	0x15600000
#define bIOPORT(Nb)	__REG(S3C2400_IOPORT_BASE_ADDR + (Nb))
#define S3C2400_PACON		0x00	/* R/W, Configures the pins of port A */
#define S3C2400_PADAT		0x04	/* R/W, Data register for port A */
#define S3C2400_PBCON		0x08	/* R/W, Configures the pins of port B */
#define S3C2400_PBDAT		0x0c	/* R/W, Data register for port B */
#define S3C2400_PBUP		0x10	/* R/W, pull-up disable register for port B */
#define S3C2400_PCCON		0x14	/* R/W, configures the pins of port C */
#define S3C2400_PCDAT		0x18	/* R/W, data register for port C */
#define S3C2400_PCUP		0x1c	/* R/W, pull-up disable register for port C */
#define S3C2400_PDCON		0x20	/* R/W, configure the pins of port D */
#define S3C2400_PDDAT		0x24	/* R/W, data register for port D */
#define S3C2400_PDUP		0x28	/* R/W, pull-up disable register for port D */
#define S3C2400_PECON		0x2c	/* R/W, configures the pins of port E */
#define S3C2400_PEDAT		0x30	/* R/W, data register for port E */
#define S3C2400_PEUP		0x34	/* R/W, pull-up disable register for port E */
#define S3C2400_PFCON		0x38	/* R/W, configure the pins of port F */
#define S3C2400_PFDAT		0x3c	/* R/W, data register for port F */
#define S3C2400_PFUP		0x40	/* R/W, pull-up disable register for port F */
#define S3C2400_PGCON		0x44	/* R/W, configures the pins of port G */
#define S3C2400_PGDAT		0x48	/* R/W, data register for port G */
#define S3C2400_PGUP		0x4c	/* R/W, pull-up disable register for port G */
#define S3C2400_OPENCR		0x50	/* R/W, open-drain enable register */
#define S3C2400_MISCCR		0x54	/* R/W, miscellaneous control register */
#define S3C2400_EXTINT		0x58	/* R/W, external interrupt control register */

#define _PACON		bIOPORT(0x00)	/* R/W, Configures the pins of port A */
#define _PADAT		bIOPORT(0x04)	/* R/W, Data register for port A */
#define _PBCON		bIOPORT(0x08)	/* R/W, Configures the pins of port B */
#define _PBDAT		bIOPORT(0x0c)	/* R/W, Data register for port B */
#define _PBUP		bIOPORT(0x10)	/* R/W, pull-up disable register for port B */
#define _PCCON		bIOPORT(0x14)	/* R/W, configures the pins of port C */
#define _PCDAT		bIOPORT(0x18)	/* R/W, data register for port C */
#define _PCUP		bIOPORT(0x1c)	/* R/W, pull-up disable register for port C */
#define _PDCON		bIOPORT(0x20)	/* R/W, configure the pins of port D */
#define _PDDAT		bIOPORT(0x24)	/* R/W, data register for port D */
#define _PDUP		bIOPORT(0x28)	/* R/W, pull-up disable register for port D */
#define _PECON		bIOPORT(0x2c)	/* R/W, configures the pins of port E */
#define _PEDAT		bIOPORT(0x30)	/* R/W, data register for port E */
#define _PEUP		bIOPORT(0x34)	/* R/W, pull-up disable register for port E */
#define _PFCON		bIOPORT(0x38)	/* R/W, configure the pins of port F */
#define _PFDAT		bIOPORT(0x3c)	/* R/W, data register for port F */
#define _PFUP		bIOPORT(0x40)	/* R/W, pull-up disable register for port F */
#define _PGCON		bIOPORT(0x44)	/* R/W, configures the pins of port G */
#define _PGDAT		bIOPORT(0x48)	/* R/W, data register for port G */
#define _PGUP		bIOPORT(0x4c)	/* R/W, pull-up disable register for port G */
#define _OPENCR		bIOPORT(0x50)	/* R/W, open-drain enable register */
#define _MISCCR		bIOPORT(0x54)	/* R/W, miscellaneous control register */
#define _EXTINT		bIOPORT(0x58)	/* R/W, external interrupt control register */

/*
 * Real Time Clock (RTC)
 */
#define _RTCCON		(*(volatile unsigned char *)0x15700040)
#define _TICNT		(*(volatile unsigned char *)0x15700044)
#define _RTCALM		(*(volatile unsigned char *)0x15700050)
#define _BCDSEC		(*(volatile unsigned char *)0x15700070)
#define _BCDMIN		(*(volatile unsigned char *)0x15700074)
#define _BCDHOUR	(*(volatile unsigned char *)0x15700078)
#define _BCDDAY		(*(volatile unsigned char *)0x1570007C)
#define _BCDDATE	(*(volatile unsigned char *)0x15700080)
#define _BCDMON		(*(volatile unsigned char *)0x15700084)
#define _BCDYEAR	(*(volatile unsigned char *)0x15700088)

/*
 * Timer
 */
#define _TCFG0		(*(volatile unsigned long *)0x15100000)
#define _TCON		(*(volatile unsigned long *)0x15100008)
#define _TCNTB4		(*(volatile unsigned long *)0x1510003C)
#define _TCNTO4		(*(volatile unsigned long *)0x15100040)