s3c2400.h.svn-base

vivi源代码

/*
 * Copyright 2001 MIZI Research Coporation.
 *
 * Copying or modifying this code for any purpose is permitted,             
 * provided that this copyright notice is preserved in its entirety        
 * in all copies or modifications.  COMPAQ COMPUTER CORPORATION           
 * MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, AS TO THE USEFULNESS       
 * OR CORRECTNESS OF THIS CODE OR ITS FITNESS FOR ANY PARTICULAR        
 * PURPOSE.                                                           
 */
/*
 * Thr 4 Oct 2001
 * Janghoon Lyu <[e-mail]> 
 */

#include "hardware.h"
#include "bitfield.h"

/*
 * Program Status Register 
 */
#define USR26_MODE		0x00
#define FIQ26_MODE		0x01
#define IRQ26_MODE		0x02
#define SVC26_MODE		0x03
#define USR_MODE		0x10
#define FIQ_MODE		0x11
#define IRQ_MODE		0x12
#define SVC_MODE		0x13
#define ABT_MODE		0x17
#define UND_MODE		0x1b
#define SYSTEM_MODE		0x1f
#define MODE_MASK		0x1f
#define F_BIT			0x40
#define I_BIT			0x80
#define CC_V_BIT		(1 << 28)
#define CC_C_BIT		(1 << 29)
#define CC_Z_BIT		(1 << 30)
#define CC_N_BIT		(1 << 31)

/*
 * Memory Controller
 */
#define DRAM_CFG_BASE		0x14000000
#define bDRAM(Nb)		__REG(DRAM_CFG_BASE + (Nb))

#define S3C2400_BWSCON		0x00	/* R/W, Bus witdth & wait status control reg. */
#define S3C2400_BANKCON0	0x04	/* R/W, Bank 0 control reg. */
#define S3C2400_BANKCON1	0x08	/* R/W, Bank 1 control reg. */
#define S3C2400_BANKCON2	0x0C	/* R/W, Bank 2 control reg. */
#define S3C2400_BANKCON3	0x10	/* R/W, Bank 3 control reg. */
#define S3C2400_BANKCON4	0x14	/* R/W, Bank 4 control reg. */
#define S3C2400_BANKCON5	0x18	/* R/W, Bank 5 control reg. */
#define S3C2400_BANKCON6	0x1C	/* R/W, Bank 6 control reg. */
#define S3C2400_BANKCON7	0x20	/* R/W, Bank 7 control reg. */
#define S3C2400_REFRESH		0x24	/* R/W, DRAM/SDRAM refresh control reg. */
#define S3C2400_BANKSIZE	0x28	/* R/W, Flexible bank size register */
#define S3C2400_MRSRB6		0x2C	/* R/W, Mode register set register bank6 */
#define S3C2400_MRSRB7		0x30	/* R/W, Mode register set register bank7 */

#define _BWSCON		bDRAM(0x00)	/* R/W, Bus witdth & wait status control reg. */
#define _BANKCON0	bDRAM(0x04)	/* R/W, Bank 0 control reg. */
#define _BANKCON1	bDRAM(0x08)	/* R/W, Bank 1 control reg. */
#define _BANKCON2	bDRAM(0x0C)	/* R/W, Bank 2 control reg. */
#define _BANKCON3	bDRAM(0x10)	/* R/W, Bank 3 control reg. */
#define _BANKCON4	bDRAM(0x14)	/* R/W, Bank 4 control reg. */
#define _BANKCON5	bDRAM(0x18)	/* R/W, Bank 5 control reg. */
#define _BANKCON6	bDRAM(0x1C)	/* R/W, Bank 6 control reg. */
#define _BANKCON7	bDRAM(0x20)	/* R/W, Bank 7 control reg. */
#define _REFRESH	bDRAM(0x24)	/* R/W, DRAM/SDRAM refresh control reg. */
#define _BANKSIZE	bDRAM(0x28)	/* R/W, Flexible bank size register */
#define _MRSRB6		bDRAM(0x2C)	/* R/W, Mode register set register bank6 */
#define _MRSRB7		bDRAM(0x30)	/* R/W, Mode register set register bank7 */

/*
 * Clock
 */
#define CLOCK_BASE	0x14800000
#define bCLOCK(Nb)	__REG(CLOCK_BASE + (Nb))
#define _LOCKTIME	bCLOCK(0x00)	/* R/W, PLL lock time count reg. */
#define _MPLLCON	bCLOCK(0x04)	/* R/W, MPLL configuration reg. */
#define _UPLLCON	bCLOCK(0x08)	/* R/W, UPLL configruation reg. */
#define _CLKCON		bCLOCK(0x0C)	/* R/W, Clock generator contron reg. */
#define _CLKSLOW	bCLOCK(0x10)	/* R/W, Slow clock control reg. */
#define _CLKDIVN	bCLOCK(0x14)	/* R/W, Clock divider control reg. */
#define S3C2400_LOCKTIME	0x00	/* R/W, PLL lock time count reg. */
#define S3C2400_MPLLCON		0x04	/* R/W, MPLL configuration reg. */
#define S3C2400_UPLLCON		0x08	/* R/W, UPLL configruation reg. */
#define S3C2400_CLKCON		0x0C	/* R/W, Clock generator contron reg. */
#define S3C2400_CLKSLOW		0x10	/* R/W, Slow clock control reg. */
#define S3C2400_CLKDIVN		0x14	/* R/W, Clock divider control reg. */

#define fPLLCON_MDIV	Fld(8,12)       /* Main divider */
#define PLLCON_MDIV	FMsk(fPLLCON_MDIV)
#define sPLLCON_MDIV(x)	FInsrt((x), fPLLCON_MDIV)
#define gPLLCON_MDIV(x)	FExtr((x), fPLLCON_MDIV)

#define fPLLCON_PDIV	Fld(6,4)        /* Pre divider */
#define PLLCON_PDIV	FMsk(fPLLCON_PDIV)
#define sPLLCON_PDIV(x)	FInsrt((x), fPLLCON_PDIV)
#define gPLLCON_PDIV(x)	FExtr((x), fPLLCON_PDIV)

#define fPLLCON_SDIV	Fld(2,0)        /* Post divider */
#define PLLCON_SDIV	FMsk(fPLLCON_SDIV)
#define sPLLCON_SDIV(x)	FInsrt((x), fPLLCON_SDIV)
#define gPLLCON_SDIV(x)	FExtr((x), fPLLCON_SDIV)

#define SPICLK		(1 << 15)       /* PCLK into SPI */
#define SPICLK_ON	(SPICLK*1)
#define SPICLK_OFF	(SPICLK*0)
#define IISCLK		(1 << 14)       /* PCLK into IIS */
#define IISCLK_ON	(IISCLK*1)
#define IISCLK_OFF	(IISCLK*0)
#define IICCLK		(1 << 13)       /* PCLK into IIC */
#define IICCLK_ON	(IICCLK*1)
#define IICCLK_OFF	(IICCLK*0)
#define ADCCLK		(1 << 12)       /* PCLK into ADC */
#define ADCCLK_ON	(ADCCLK*1)
#define ADCCLK_OFF	(ADCCLK*0)
#define RTCCLK		(1 << 11)       /* PCLK into RTC */
#define RTCCLK_ON	(RTCCLK*1)
#define RTCCLK_OFF	(RTCCLK*0)
#define GPIOCLK		(1 << 10)       /* PCLK into GPIO */
#define GPIOCLK_ON	(GPIOCLK*1)
#define GPIOCLK_OFF	(GPIOCLK*0)
#define UART1CLK	(1 << 9)        /* PCLK into UART1 */
#define UART1LCK_ON	(UART1CLK*1)
#define UART1CLK_OFF	(UART1CLK*0)
#define UART0CLK	(1 << 8)        /* PCLK into UART0 */
#define UART0CLK_ON	(UART0CLK*1)
#define UART0CLK_OFF	(UART0CLK*0)
#define MMCCLK		(1 << 7)        /* PCLK into MMC */
#define MMCCLK_ON	(MMCCLK*1)
#define MMCCLK_OFF	(MMCCLK*1)
#define PWMTIMERCLK	(1 << 6)        /* PCLK into PWMTIMER */
#define PWMTIMERCLK_ON	(PWMTIMERCLK*1)
#define PWMTIMERCLK_OFF	(PWMTIMERCLK*0)
#define USBDCLK		(1 << 5)        /* PCLK into USB device */
#define USBDCLK_ON	(USBDCLK*1)
#define USBDCLK_OFF	(USBDCLK*0)
#define USBHCLK		(1 << 4)        /* HCLK into USB Host */
#define USBHCLK_ON	(USBHCLK*1)
#define USBHCLK_OFF	(USBHCLK*0)
#define LCDCCLK		(1 << 3)        /* HCLK into LCDC */
#define LCDCCLK_ON	(LCDCCLK*1)
#define LCDCCLK_OFF	(LCDCCLK*0)
#define IDLE_MODE	(1 << 2)        /* Enter IDLE mode */
#define SL_IDLE_MODE	(1 << 1)        /* Enter SL_IDLE mode (set CLKCON to 0xe) */
#define STOP_MODE	(1 << 0)        /* Enter STOP mode */


/*
 * UART
 */
#define UART_CTL_BASE		0x15000000
#define UART0_CTL_BASE		0x15000000	/* UART channel 0 */
#define UART1_CTL_BASE		0x15004000	/* UART channel 1 */
#define bUART(x, Nb)		__REGl(UART_CTL_BASE + (x)*0x4000 + (Nb))
#define bUARTb(x, Nb)		__REGb(UART_CTL_BASE + (x)*0x4000 + (Nb))
#if 0
#define S3C2400_ULCON		0x00	/* R/W */
#define S3C2400_UCON		0x04	/* R/W */
#define S3C2400_UFCON		0x08	/* R/W */
#define S3C2400_UMCON		0x0C	/* R/W */
#define S3C2400_UTRSTAT		0x10	/* R */
#define S3C2400_UERSTAT		0x14	/* R */
#define S3C2400_UFSTAT		0x18	/* R */
#define S3C2400_UMSTAT		0x1C	/* R */
#define S3C2400_UTXH		0x20	/* W, by byte, little endian */
#define S3C2400_URXH		0x24	/* R, by byte, little endian */
#define S3C2400_UBRDIV		0x28	/* R/W */
#endif
/* Offset */
#define oULCON			0x00	/* R/W */
#define oUCON			0x04	/* R/W */
#define oUFCON			0x08	/* R/W */
#define oUMCON			0x0C	/* R/W */
#define oUTRSTAT		0x10	/* R */
#define oUERSTAT		0x14	/* R */
#define oUFSTAT			0x18	/* R */
#define oUMSTAT			0x1C	/* R */
#define oUTXH			0x20	/* W, by byte, little endian */
#define oURXH			0x24	/* R, by byte, little endian */
#define oUBRDIV			0x28	/* R/W */

#if 0
#define S3C2400_ULCON_5BITS	0x0
#define S3C2400_ULCON_6BITS	0x1
#define S3C2400_ULCON_7BITS	0x2
#define S3C2400_ULCON_8BITS	0x3
#endif

#if 0
#define UCON_TXINT_PULSE	(0 << 9)
#define UCON_TXINT_LEVEL	(1 << 9)
#define UCON_RXINT_PULSE	(0 << 8)
#define UCON_RXINT_LEVEL	(1 << 8)
#define UCON_RX_TIMEOUT_EN	(1 << 7)
#define UCON_ERR_INT_EN		(1 << 6)
#define UCON_LOOPBACK		(1 << 5)
#define UCON_BRKSIG		(1 << 4)