sa1100.h.svn-base

vivi源代码

#define SA1100_PPCR_73MHZ	1
#define SA1100_PPCR_88MHZ	2
#define SA1100_PPCR_103MHZ	3
#define SA1100_PPCR_118MHZ	4
#define SA1100_PPCR_132MHZ	5
#define SA1100_PPCR_147MHZ	6
#define SA1100_PPCR_162MHZ	7
#define SA1100_PPCR_176MHZ	8
#define SA1100_PPCR_191MHZ	9
#define SA1100_PPCR_206MHZ	10
#define SA1100_PPCR_221MHZ	11

#define SA1100_PPDR_REG   	0x90060000	/* PPC Pin Direction Reg.          */
#define SA1100_PPDR_LFCLK 	0x400

#define SA1100_PPSR_REG   	0x90060004	/* PPC Pin State Reg.              */

#define	SA1100_GPIO_BASE	(0x90040000)
#define	SA1100_GPIO_GPLR_OFF	(0)
#define	SA1100_GPIO_GPDR_OFF	(4)
#define	SA1100_GPIO_GPSR_OFF	(8)
#define	SA1100_GPIO_GPCR_OFF	(0xc)
#define	SA1100_GPIO_GRER_OFF	(0x10)
#define	SA1100_GPIO_GFER_OFF	(0x14)
#define	SA1100_GPIO_GEDR_OFF	(0x18)
#define	SA1100_GPIO_GAFR_OFF	(0x1c)

#define GPLR			__REG(SA1100_GPIO_BASE+SA1100_GPIO_GPLR_OFF)


#define	SA1100_GPIO_SET(off, bits)  \
    ((*((volatile unsigned long *)(((char*)SA1100_GPIO_BASE)+(off))))|=(bits))

#define	SA1100_GPIO_CLR(off, bits)  \
    ((*((volatile unsigned long *)(((char*)SA1100_GPIO_BASE)+(off))))&=~(bits))

#define	SA1100_GPIO_READ(off)  \
    (*((volatile unsigned long *)(((char*)SA1100_GPIO_BASE)+(off))))

#define	SA1100_GPIO_WRITE(off, v)  \
    ((*((volatile unsigned long *)(((char*)SA1100_GPIO_BASE)+(off)))) = (v))

#define	SA1100_GPIO_GAFR_LCD_BITS   (0xff << 2)
#define	SA1100_GPIO_GPDR_LCD_BITS   (0xff << 2)

#define	SA1100_GPIO_GPLR_READ()	    SA1100_GPIO_READ(SA1100_GPIO_GPLR_OFF)
#define	SA1100_GPIO_GPDR_READ()	    SA1100_GPIO_READ(SA1100_GPIO_GPDR_OFF)
#define	SA1100_GPIO_GPSR_READ()	    SA1100_GPIO_READ(SA1100_GPIO_GPSR_OFF)
#define	SA1100_GPIO_GPCR_READ()	    SA1100_GPIO_READ(SA1100_GPIO_GPCR_OFF)
#define	SA1100_GPIO_GRER_READ()	    SA1100_GPIO_READ(SA1100_GPIO_GRER_OFF)
#define	SA1100_GPIO_GFER_READ()	    SA1100_GPIO_READ(SA1100_GPIO_GFER_OFF)
#define	SA1100_GPIO_GEDR_READ()	    SA1100_GPIO_READ(SA1100_GPIO_GEDR_OFF)
#define	SA1100_GPIO_GAFR_READ()	    SA1100_GPIO_READ(SA1100_GPIO_GAFR_OFF)

#define	SA1100_GPIO_GPLR_WRITE(v)   SA1100_GPIO_WRITE(SA1100_GPIO_GPLR_OFF,v)
#define	SA1100_GPIO_GPDR_WRITE(v)   SA1100_GPIO_WRITE(SA1100_GPIO_GPDR_OFF,v)
#define	SA1100_GPIO_GPSR_WRITE(v)   SA1100_GPIO_WRITE(SA1100_GPIO_GPSR_OFF,v)
#define	SA1100_GPIO_GPCR_WRITE(v)   SA1100_GPIO_WRITE(SA1100_GPIO_GPCR_OFF,v)
#define	SA1100_GPIO_GRER_WRITE(v)   SA1100_GPIO_WRITE(SA1100_GPIO_GRER_OFF,v)
#define	SA1100_GPIO_GFER_WRITE(v)   SA1100_GPIO_WRITE(SA1100_GPIO_GFER_OFF,v)
#define	SA1100_GPIO_GEDR_WRITE(v)   SA1100_GPIO_WRITE(SA1100_GPIO_GEDR_OFF,v)
#define	SA1100_GPIO_GAFR_WRITE(v)   SA1100_GPIO_WRITE(SA1100_GPIO_GAFR_OFF,v)

#define	SA1100_GPIO_GPLR_SET(v)	    SA1100_GPIO_SET(SA1100_GPIO_GPLR_OFF,v)
#define	SA1100_GPIO_GPDR_SET(v)	    SA1100_GPIO_SET(SA1100_GPIO_GPDR_OFF,v)
#define	SA1100_GPIO_GPSR_SET(v)	    SA1100_GPIO_SET(SA1100_GPIO_GPSR_OFF,v)
#define	SA1100_GPIO_GPCR_SET(v)	    SA1100_GPIO_SET(SA1100_GPIO_GPCR_OFF,v)
#define	SA1100_GPIO_GRER_SET(v)	    SA1100_GPIO_SET(SA1100_GPIO_GRER_OFF,v)
#define	SA1100_GPIO_GFER_SET(v)	    SA1100_GPIO_SET(SA1100_GPIO_GFER_OFF,v)
#define	SA1100_GPIO_GEDR_SET(v)	    SA1100_GPIO_SET(SA1100_GPIO_GEDR_OFF,v)
#define	SA1100_GPIO_GAFR_SET(v)	    SA1100_GPIO_SET(SA1100_GPIO_GAFR_OFF,v)

#define	SA1100_GPIO_GPLR_CLR(v)	    SA1100_GPIO_CLR(SA1100_GPIO_GPLR_OFF,v)
#define	SA1100_GPIO_GPDR_CLR(v)	    SA1100_GPIO_CLR(SA1100_GPIO_GPDR_OFF,v)
#define	SA1100_GPIO_GPSR_CLR(v)	    SA1100_GPIO_CLR(SA1100_GPIO_GPSR_OFF,v)
#define	SA1100_GPIO_GPCR_CLR(v)	    SA1100_GPIO_CLR(SA1100_GPIO_GPCR_OFF,v)
#define	SA1100_GPIO_GRER_CLR(v)	    SA1100_GPIO_CLR(SA1100_GPIO_GRER_OFF,v)
#define	SA1100_GPIO_GFER_CLR(v)	    SA1100_GPIO_CLR(SA1100_GPIO_GFER_OFF,v)
#define	SA1100_GPIO_GEDR_CLR(v)	    SA1100_GPIO_CLR(SA1100_GPIO_GEDR_OFF,v)
#define	SA1100_GPIO_GAFR_CLR(v)	    SA1100_GPIO_CLR(SA1100_GPIO_GAFR_OFF,v)

/*
 * power management reggies
 */

#define	SA1100_PMCR 0x90020000	/* Power manager control register */
#define	SA1100_PSSR 0x90020004	/* Power manager sleep status register */
#define	SA1100_PSPR 0x90020008	/* Power manager scratch pad register */
#define	SA1100_PWER 0x9002000C	/* Power manager wake-up enable register */
#define	SA1100_PCFR 0x90020010	/* Power manager general configuration reg */
#define	PCFR_OPDE   (1<<0)	/* power down 3.6MHz osc */
#define	PCFR_FP	    (1<<1)	/* float PCMCIA controls during sleep */
#define	PCFR_FS	    (1<<2)	/* float static chip selects during sleep */
#define	PCFR_FO	    (1<<3)	/* force 32KHz osc enable on */

#define	SA1100_PPCR 0x90020014 /* Power manager PLL configuration register */
#define	SA1100_PGSR 0x90020018 /* Power manager GPIO sleep state register */
#define	SA1100_POSR 0x9002001C /* Power manager oscillator status register */


#define RSRR		__REG(0x90030000)
#define RCSR		__REG(0x90030004)
#define	RSRR_SWR    0x00000001	/* software reset bit */
#define SA1100_RSRR 0x90030000 /* Reset controller software reset register */
#define SA1100_RCSR 0x90030004 /* Reset controller status register */


#define	SA1100_ICIP 0x90050000	/* interrupt controller IRQ pend reg */
#define	SA1100_ICFP 0x90050010	/* interrupt controller FIQ pend reg */
#define	SA1100_ICMR 0x90050004	/* interrupt controller mask reg */
#define	SA1100_ICLR 0x90050008	/* interrupt controller level reg */
#define	SA1100_ICCR 0x9005000C	/* interrupt controller control reg */

#define	SA1100_RTAR 0x90010000	/* RTC alarm reg */
#define	SA1100_RCNR 0x90010004	/* RTC count reg */
#define	SA1100_RTTR 0x90010008	/* RTC timer trim reg */
#define	SA1100_RTSR 0x90010010	/* RTC status reg */

/*
 * Operating System (OS) timer control registers
 *
 * Registers
 *    OSMR0             Operating System (OS) timer Match Register 0
 *                      (read/write).
 *    OSMR1             Operating System (OS) timer Match Register 1
 *                      (read/write).
 *    OSMR2             Operating System (OS) timer Match Register 2
 *                      (read/write).
 *    OSMR3             Operating System (OS) timer Match Register 3
 *                      (read/write).
 *    OSCR              Operating System (OS) timer Counter Register
 *                      (read/write).
 *    OSSR              Operating System (OS) timer Status Register
 *                      (read/write).
 *    OWER              Operating System (OS) timer Watch-dog Enable Register
 *                      (read/write).
 *    OIER              Operating System (OS) timer Interrupt Enable Register
 *                      (read/write).
 */

#define OSMR0           __REG(0x90000000)  /* OS timer Match Reg. 0 */
#define OSMR1           __REG(0x90000004)  /* OS timer Match Reg. 1 */
#define OSMR2           __REG(0x90000008)  /* OS timer Match Reg. 2 */
#define OSMR3           __REG(0x9000000c)  /* OS timer Match Reg. 3 */
#define OSCR            __REG(0x90000010)  /* OS timer Counter Reg. */
#define OSSR            __REG(0x90000014)  /* OS timer Status Reg. */
#define OWER            __REG(0x90000018)  /* OS timer Watch-dog Enable Reg. */
#define OIER            __REG(0x9000001C)  /* OS timer Interrupt Enable Reg. */

#define OSSR_M(Nb)                      /* Match detected [0..3]           */ \
                        (0x00000001 << (Nb))
#define OSSR_M0         OSSR_M (0)      /* Match detected 0                */
#define OSSR_M1         OSSR_M (1)      /* Match detected 1                */
#define OSSR_M2         OSSR_M (2)      /* Match detected 2                */
#define OSSR_M3         OSSR_M (3)      /* Match detected 3                */

#define OWER_WME        0x00000001      /* Watch-dog Match Enable          */
                                        /* (set only)                      */

#define OIER_E(Nb)                      /* match interrupt Enable [0..3]   */ \
                        (0x00000001 << (Nb))
#define OIER_E0         OIER_E (0)      /* match interrupt Enable 0        */
#define OIER_E1         OIER_E (1)      /* match interrupt Enable 1        */
#define OIER_E2         OIER_E (2)      /* match interrupt Enable 2        */
#define OIER_E3         OIER_E (3)      /* match interrupt Enable 3        */

/*
 * Real-Time Clock (RTC) control registers
 *
 * Registers
 *    RTAR              Real-Time Clock (RTC) Alarm Register (read/write).
 *    RCNR              Real-Time Clock (RTC) CouNt Register (read/write).
 *    RTTR              Real-Time Clock (RTC) Trim Register (read/write).
 *    RTSR              Real-Time Clock (RTC) Status Register (read/write).
 *
 * Clocks
 *    frtx, Trtx        Frequency, period of the real-time clock crystal
 *                      (32.768 kHz nominal).
 *    frtc, Trtc        Frequency, period of the real-time clock counter
 *                      (1 Hz nominal).
 */

#define RTAR            __REG(0x90010000)  /* RTC Alarm Reg. */
#define RCNR            __REG(0x90010004)  /* RTC CouNt Reg. */
#define RTTR            __REG(0x90010008)  /* RTC Trim Reg. */
#define RTSR            __REG(0x90010010)  /* RTC Status Reg. */

#define RTTR_C          Fld (16, 0)     /* clock divider Count - 1         */
#define RTTR_D          Fld (10, 16)    /* trim Delete count               */
                                        /* frtc = (1023*(C + 1) - D)*frtx/ */
                                        /*        (1023*(C + 1)^2)         */
                                        /* Trtc = (1023*(C + 1)^2)*Trtx/   */
                                        /*        (1023*(C + 1) - D)       */

#define RTSR_AL         0x00000001      /* ALarm detected                  */
#define RTSR_HZ         0x00000002      /* 1 Hz clock detected             */
#define RTSR_ALE        0x00000004      /* ALarm interrupt Enable          */
#define RTSR_HZE        0x00000008      /* 1 Hz clock interrupt Enable     */