fulladd.v

Full adder using Verilog

// FullAdd.V
module  fulladd(in1, in2, carryin, sum, carryout);
input   in1, in2, carryin;
output  sum, carryout;
wire    sum, carryout;
  assign  {carryout, sum} = in1 + in2 + carryin;
endmodule