📄 a8_mf6210_rx_hk.asm
字号:
; LDA !BP0
; AND #USER_BIT4_INV ;SET SPI_SS -->LOW
; STA !BP0
LDA #7
STA CUR_REG
LDA #12H
STA DATA_H
LDA #10H ;2.418GHz
STA DATA_L
JSR WRITE_1REG_2DATA_OPERATION
JSR DELAY
Q_IDLE_MODE:
RTS
;------------------------------------------------
;------------------------------------
INIT_RFIC_REG:
LDA #0
STA COUNT
INIT_RFIC_REG_10:
LDA COUNT
TAX
LDA TABLE_RFIC_REG,X
STA CUR_REG
INC COUNT
LDA COUNT
TAX
LDA TABLE_RFIC_REG,X
STA DATA_H
INC COUNT
LDA COUNT
TAX
LDA TABLE_RFIC_REG,X
STA DATA_L
INC COUNT
LDA CUR_REG
CMP #FFH
BEQ Q_INIT_RFIC_REG
JSR WRITE_1REG_2DATA_OPERATION
LDA !BP0
AND #USER_BIT6_INV
STA !BP0
JSR DELAY_10US
JMP INIT_RFIC_REG_10
Q_INIT_RFIC_REG:
LDA !BP0
AND #USER_BIT6_INV
STA !BP0
RTS
;-----------------------------------------------
;------------------------------------------------------------------
;@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
;------------------------------------------------------------------
ENABLE_TMG1_40MS:
LDA #0
STA TMG1_L
STA TMG1_H
STA TMG1_SET_FLAG
LDA #0
STA TMG1_COUNT_H
LDA #40
STA TMG1_COUNT_L
LDA #94 ;==> 1ms for 1 cycle
STA !TMG1V
LDA #00000101B
STA !TMG1C ;FSYS/64 (FROM 10.667us to 2.7ms)
LDA !IEF0
ORA #01000000B
STA !IEF0 ;ENABLE TMG1 INTERRUPT
Q_ENABLE_TMG1_40MS:
RTS
;------------------------------------
INIT_FRAMER_REG:
LDA #0
STA COUNT
INIT_FRAMER_REG_10:
LDA COUNT
TAX
LDA TABLE_FRAMER_REG,X
STA CUR_REG
INC COUNT
LDA COUNT
TAX
LDA TABLE_FRAMER_REG,X
STA DATA_H
INC COUNT
LDA COUNT
TAX
LDA TABLE_FRAMER_REG,X
STA DATA_L
INC COUNT
LDA CUR_REG
CMP #FFH
BEQ Q_INIT_FRAMER_REG
JSR WRITE_1REG_2DATA_OPERATION
LDA !BP0
AND #USER_BIT6_INV
STA !BP0
JSR DELAY_10US
JMP INIT_FRAMER_REG_10
Q_INIT_FRAMER_REG:
LDA !BP0
AND #USER_BIT6_INV
STA !BP0
RTS
DELAY:
; NOP
; NOP
; NOP
RTS
;-------------------------------------
;-----------------------------------------------
WRITE_1REG_2DATA_OPERATION:
;INPUT: CUR_REG, DATA_H, DATA_L
LDA !BP0
AND #USER_BIT4_INV ;SPI_SS
AND #USER_BIT6_INV ;SPI_CLK
AND #USER_BIT5_INV ;SPI_MOSI
STA !BP0
; JSR DELAY
NOP
;--- WRITE REG --------
LDA #8 ;
STA BIT_CNT
WRITE_1REG_2DATA_OPERATION_40:
CLC
ROL CUR_REG
BCC WRITE_1REG_2DATA_OPERATION_42
WRITE_1REG_2DATA_OPERATION_41:
JSR SEND_BIT1
JMP WRITE_1REG_2DATA_OPERATION_50
WRITE_1REG_2DATA_OPERATION_42:
JSR SEND_BIT0
;-----------
WRITE_1REG_2DATA_OPERATION_50:
LDA BIT_CNT
DEC A
STA BIT_CNT
CMP #0
BEQ WRITE_1REG_2DATA_OPERATION_60
JMP WRITE_1REG_2DATA_OPERATION_40
;----- WRITE DATA_H --------
WRITE_1REG_2DATA_OPERATION_60:
LDA #8 ;
STA BIT_CNT
WRITE_1REG_2DATA_OPERATION_140:
CLC
ROL DATA_H
BCC WRITE_1REG_2DATA_OPERATION_142
WRITE_1REG_2DATA_OPERATION_141:
JSR SEND_BIT1
JMP WRITE_1REG_2DATA_OPERATION_150
WRITE_1REG_2DATA_OPERATION_142:
JSR SEND_BIT0
;-----------
WRITE_1REG_2DATA_OPERATION_150:
LDA BIT_CNT
DEC A
STA BIT_CNT
CMP #0
BEQ WRITE_1REG_2DATA_OPERATION_160
JMP WRITE_1REG_2DATA_OPERATION_140
;----- WRITE DATA_L --------
WRITE_1REG_2DATA_OPERATION_160:
; LDA !BP0
; ORA #USER_BIT4
; AND #USER_BIT6_INV
; STA !BP0
; JSR DELAY_10US
; JSR DELAY_10US
; JSR DELAY_10US
; LDA !BP0
; AND #USER_BIT4_INV
; STA !BP0
LDA !BP0
AND #USER_BIT6_INV
STA !BP0
; JSR DELAY
NOP
LDA #8 ;
STA BIT_CNT
WRITE_1REG_2DATA_OPERATION_240:
CLC
ROL DATA_L
BCC WRITE_1REG_2DATA_OPERATION_242
WRITE_1REG_2DATA_OPERATION_241:
JSR SEND_BIT1
JMP WRITE_1REG_2DATA_OPERATION_250
WRITE_1REG_2DATA_OPERATION_242:
JSR SEND_BIT0
;-----------
WRITE_1REG_2DATA_OPERATION_250:
LDA BIT_CNT
DEC A
STA BIT_CNT
CMP #0
BEQ WRITE_1REG_2DATA_OPERATION_260
JMP WRITE_1REG_2DATA_OPERATION_240
WRITE_1REG_2DATA_OPERATION_260:
JSR DUMMY_PULSE
LDA !BP0
ORA #USER_BIT4 ;SPI_SS ---> HIGH
; AND #USER_BIT6_INV
STA !BP0
; JSR DELAY
NOP
Q_WRITE_1REG_2DATA_OPERATION:
RTS
;-----------------------------------------
DUMMY_PULSE:
LDA !BP0
AND #USER_BIT6_INV
STA !BP0
; JSR DELAY
NOP
LDA !BP0
ORA #USER_BIT6
STA !BP0
; JSR DELAY
NOP
LDA !BP0
AND #USER_BIT6_INV
STA !BP0
; JSR DELAY
NOP
Q_DUMMY_PULSE:
RTS
;-----------------------------------------
SEND_BIT1:
LDA !BP0
ORA #USER_BIT5
AND #USER_BIT6_INV
STA !BP0
; JSR DELAY
NOP
LDA !BP0
ORA #USER_BIT6
STA !BP0
; JSR DELAY
NOP
Q_SEND_BIT1:
RTS
;------------------------------------------
SEND_BIT0:
LDA !BP0
AND #USER_BIT5_INV
AND #USER_BIT6_INV
STA !BP0
; JSR DELAY
NOP
LDA !BP0
ORA #USER_BIT6
STA !BP0
; JSR DELAY
NOP
Q_SEND_BIT0:
RTS
;------------------------------------------
;------------------------------------------------------------------
ENABLE_TMG1_140MS:
LDA #0
STA TMG1_L
STA TMG1_H
STA TMG1_SET_FLAG
LDA #0
STA TMG1_COUNT_H
LDA #140
STA TMG1_COUNT_L
LDA #94 ;==> 1ms for 1 cycle
STA !TMG1V
LDA #00000101B
STA !TMG1C ;FSYS/64 (FROM 10.667us to 2.7ms)
LDA !IEF0
ORA #01000000B
STA !IEF0 ;ENABLE TMG1 INTERRUPT
Q_ENABLE_TMG1_140MS:
RTS
;-----------------------------------------------------------------
;---------------------------------
DISABLE_TMG1:
LDA !TMG1C
AND #11111110B
STA !TMG1C
LDA !IEF0
AND #10111111B
STA !IEF0
RTS
;-----------------------------------
;---------------------------------
ENABLE_FXF15:
LDA !IEF1
ORA #00000010B
STA !IEF1 ;ENABLE FXF15 INTERRUPT
RTS
;----------------------------------
DISABLE_FXF15:
LDA !IEF1
AND #11111101B
STA !IEF1 ;DISABLE FXF15 INTERRUPT
RTS
;-------------------------------
;-------------------------------------
DELAY_5US:
;--- NOP = 0.167uS (UNDER 6MHz) ----
LDA #1
STA DV_R0
DELAY_5US_1:
LDA DV_R0 ;4 CYCLES
DEC A ;2 CYCLES
STA DV_R0 ;4 CYCLES
CMP #0 ;2 CYCLES
BNE DELAY_5US_1 ;3 CYCLES
RTS
;-------------------------------
DELAY_10US:
;--- NOP = 0.167uS (UNDER 6MHz) ----
LDA #2
STA DV_R0
DELAY_10US_1:
LDA DV_R0 ;4 CYCLES
DEC A ;2 CYCLES
STA DV_R0 ;4 CYCLES
CMP #0 ;2 CYCLES
BNE DELAY_10US_1 ;3 CYCLES
RTS
;-----------------------
DELAY_50US:
JSR DELAY_10US
JSR DELAY_10US
JSR DELAY_10US
JSR DELAY_10US
JSR DELAY_10US
RTS
;-----------------------
DELAY_100US:
; LDA #39 ;
LDA #38
STA DV_R0
DELAY_100US_1:
LDA DV_R0 ;4 CYCLES
DEC A ;2 CYCLES
STA DV_R0 ;4 CYCLES
CMP #0 ;2 CYCLES
BNE DELAY_100US_1 ;3 CYCLES
Q_DELAY_100US:
RTS
;---------------------------------
DELAY_1MS:
JSR DELAY_100US
JSR DELAY_100US
JSR DELAY_100US
JSR DELAY_100US
JSR DELAY_100US
JSR DELAY_100US
JSR DELAY_100US
JSR DELAY_100US
JSR DELAY_100US
JSR DELAY_100US
Q_DELAY_1MS:
RTS
;------------------------
DELAY_5MS:
JSR DELAY_1MS
JSR DELAY_1MS
JSR DELAY_1MS
JSR DELAY_1MS
JSR DELAY_1MS
Q_DELAY_5MS:
RTS
;-------------------------
DELAY_10MS:
JSR DELAY_1MS
JSR DELAY_1MS
JSR DELAY_1MS
JSR DELAY_1MS
JSR DELAY_1MS
JSR DELAY_1MS
JSR DELAY_1MS
JSR DELAY_1MS
JSR DELAY_1MS
JSR DELAY_1MS
Q_DELAY_10MS:
RTS
;-----------------------
DELAY_100MS:
JSR DELAY_10MS
JSR DELAY_10MS
JSR DELAY_10MS
JSR DELAY_10MS
JSR DELAY_10MS
JSR DELAY_10MS
JSR DELAY_10MS
JSR DELAY_10MS
JSR DELAY_10MS
JSR DELAY_10MS
Q_DELAY_100MS:
RTS
;------------------------
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