a8_mf6210_rx_hk.asm

用W588D写的驱动6210-2.4G无线模块,收发程序在一块,(65C02汇编指令实现)

;==========================================================================
;=============================== TABLE ====================================
;==========================================================================
TABLE_FRAMER_REG: ;(reg48 ~ reg57)
	DB	30H, 98H, 00H 	;REG48
	DB	31H, FFH, 8FH	;REG49
	DB	32H, 80H, 18H	;REG50
	DB	33H, 80H, 56H	;REG51
	DB	34H, 4EH, F6H	;REG52
	DB	35H, F6H, F5H	;REG53
	DB	36H, 18H, 5CH	;REG54
	DB	37H, D6H, 51H	;REG55
	DB	38H, 44H, 44H	;REG56
	DB	39H, E0H, 00H	;REG57
	DB	FFH, FFH, FFH	;--------(END)
TABLE_RFIC_REG: ; (reg00 ~ reg28)
	DB	09H, 21H, 82H	;REG9	
	DB	00H, 35H, 4DH	;REG0
	DB	02H, 1EH, 01H	;REG2
	DB	04H, BCH, F0H	;REG4
	DB	05H, 00H, A1H	;REG5
	DB	07H, 12H, 4CH
;	DB	07H, 13H, 4CH	;REG7				;TX
	DB	08H, 80H, 00H	;REG8
	DB	0AH, 00H, 04H	;REG10
	DB	0BH, 40H, 41H	;REG11
	DB	0CH, 80H, 00H	;REG12
	DB	0DH, 00H, 00H	;REG13
	DB	0EH, 16H, 9DH	;REG14
	DB	0FH, 90H, ADH	;REG15
	DB	10H, B0H, 00H	;REG16
	DB	12H, E0H, 00H	;REG18
	DB	13H, A1H, 14H	;REG19
	DB	14H, 81H, 95H	;REG20
	DB	15H, 69H, 62H	;REG21
	DB	16H, 00H, 02H	;REG22
	DB	17H, 00H, 02H	;REG23
	DB	18H, B1H, 40H	;REG24
	DB	19H, A8H, 0FH	;REG25
	DB	1AH, 3EH, 04H	;REG26
	DB	1CH, 58H, 00H	;REG28
	DB	FFH, FFH, FFH	;-------(END)
;===================================================
;===== FIND_RSSI ===================================
;===================================================
;O/P : RETURN_FLAG; ID; RSSI_VALUE
FIND_RSSI:
	JSR	ENABLE_TMG1_40MS

FIND_RSSI_11:
	JSR	SET_REG82_RX	; CLR_R_PTR
	NOP
FIND_RSSI_12:
;-----------------------------------------------
	JSR RX_CONTROL		; SET WORKING AS RX
	NOP
FIND_RSSI_13:
;	LDA TMG1_SET_FLAG
;	CMP	#1
;	BNE	FIND_RSSI_14

;	JMP	FIND_RSSI_200
FIND_RSSI_14:
	JSR	READ_REG

	LDA DATA_H
	AND	#F0H
	CMP	#D0H
	BNE	FIND_RSSI_12

	LDA DATA_H
	AND	#USER_BIT2
	BEQ	FIND_RSSI_13
	NOP
	JSR	READ_2BYTE_RSSI

FIND_RSSI_15:
	LDA TMG1_SET_FLAG
	CMP	#1
	BNE	FIND_RSSI_16

	JMP	FIND_RSSI_200
FIND_RSSI_16:
	LDA !BP0
	AND	#USER_BIT1
	BEQ FIND_RSSI_15

	JSR	READ_255BYTE_DATA

	LDA RX_BYTE_2
	CMP	#0
	BEQ FIND_RSSI_200
;-------------------------
FIND_RSSI_100:				;-----RECEIVED A DATA
	
	LDA RX_BYTE_2	
	AND	#00000011B
	STA ID					; O/P --- ID
	
	LDA #1
	STA RETURN_FLAG			; O/P --- RETURN_FLAG
	
	LDA RSSI_VALUE			; O/P ---- RSSI_VALUE
	STA RSSI_VALUE
	JSR DISABLE_TMG1

	JMP	Q_FIND_RSSI
;-------------------------
FIND_RSSI_200:			;-----NO DATA RECEIVED

	LDA #0
	STA RETURN_FLAG
	STA ID
	STA RSSI_VALUE

	JSR DISABLE_TMG1

Q_FIND_RSSI:
	RTS
;======================================================
;======= OTHER SUBS ===================================
;======================================================
;-----------------------------------------
;O/P : DATA_H, DATA_L
READ_2BYTE_RSSI:
	LDA #6
	STA CUR_REG

	LDA CUR_REG
	ORA #USER_BIT7
	STA	CUR_REG

	LDA !BP0
	AND	#USER_BIT4_INV
	STA !BP0
	NOP

	JSR	WRITE_CUR_REG
	NOP
	
	JSR READ_REG_DATA	;


	JSR	DUMMY_PULSE

	LDA !BP0
	ORA #USER_BIT4
	STA !BP0
	NOP


	NOP
	LDA DATA_H
	LSR	A
	LSR	A
	STA RSSI_VALUE


Q_READ_2BYTE_RSSI:
	RTS


;-------------------------------------------




;--------------------------------------------

READ_255BYTE_DATA:

	LDA #80
	STA CUR_REG

	LDA #0
	STA DATA_H
	STA DATA_L
	STA RX_BYTE_2
	STA RX_BYTE_1

	LDA CUR_REG
	ORA #USER_BIT7
	STA	CUR_REG


	LDA !BP0
	AND	#USER_BIT4_INV
	STA !BP0

	JSR	DELAY

	JSR	WRITE_CUR_REG
	JSR	DELAY


	JSR READ_REG_DATA	;BYTE 1, 2
	NOP
	LDA DATA_H
	STA RX_BYTE_1		; STORE PACKET LENGHT
	LDA DATA_L
	STA RX_BYTE_2		; STORE MY_ID

	LDA #0
	STA DATA_H
	STA DATA_L



	LDA #0
	STA PACKET_COUNT


READ_XX:


;-----
	JSR READ_REG_DATA	;BYTE 3,4 ARE DUMMY DATA
	NOP
	LDA DATA_H
	STA RX_BYTE_3
	LDA DATA_L
	STA RX_BYTE_4

	LDA #0
	STA DATA_H
	STA DATA_L

	LDA PACKET_COUNT
	INC	A
	STA PACKET_COUNT

	CMP	#31
	BEQ	READ_YY

	JMP	READ_XX

READ_YY:
;-----
	JSR	DUMMY_PULSE

	LDA !BP0
	ORA #USER_BIT4
	STA !BP0
	NOP
	JSR	DELAY
	
	JSR	DELAY


Q_READ_10BYTE_DATA:
	RTS

;--------------------------------------------------------
READ_REG:

;	LDA #07H	;-------reg7
	LDA #64
	STA CUR_REG
	LDA #0
	STA DATA_H
	STA DATA_L

	LDA CUR_REG
	ORA #USER_BIT7
	STA	CUR_REG


	LDA !BP0
	AND	#USER_BIT4_INV
	STA !BP0

	NOP
	JSR	WRITE_CUR_REG

	NOP
	
	JSR READ_REG_DATA

	NOP

	JSR	DUMMY_PULSE

	LDA !BP0
	ORA #USER_BIT4
	STA !BP0

Q_READ_REG:
	RTS
;--------------------------------------------------
READ_REG_DATA:
; O/P : DATA_H, DATA_L
;	LDA #16

	LDA	#0
	STA DATA_PT

	LDA #0
	STA DATA_H
	STA DATA_L
	
	

READ_REG_DATA_10:
	JSR	CLK_LOW

	JSR	CLK_HIGH

	LDA RETURN_FLAG
	CMP	#1
	BNE Q_READ_REG_DATA

	LDA !BP0
	AND	#USER_BIT6_INV
	STA !BP0
	NOP
	JMP	READ_REG_DATA_10

Q_READ_REG_DATA:
	RTS

;-------------------------------------------
CLK_LOW:

	LDA !BP0
	AND	#USER_BIT6_INV
	STA !BP0

	NOP


Q_CLK_LOW:
	RTS
;----------------------------------------------
CLK_HIGH:


	LDA !BP0
	ORA #USER_BIT6
	STA !BP0
	NOP


	LDA !BP0
	AND	#USER_BIT2
	BEQ CLK_HIGH_20

CLK_HIGH_10:
	JSR	READ_BIT1
	JMP	CLK_HIGH_30

CLK_HIGH_20:
	JSR	READ_BIT0

CLK_HIGH_30:
	JSR	DELAY


Q_CLK_HIGH:
	RTS


;------------------------------------------------------

READ_BIT1:

	SEC
	ROL DATA_L
	ROL	DATA_H


	LDA DATA_PT
	INC	A
	STA DATA_PT
	CMP	#16
	BEQ	READ_BIT1_200

RREAD_BIT1_100:
	LDA	#1
	STA RETURN_FLAG
	JMP	Q_READ_BIT1
READ_BIT1_200:
	LDA	#0
	STA RETURN_FLAG

	
Q_READ_BIT1:
	RTS
;------------------------------------------------

READ_BIT0:

	CLC
	ROL DATA_L
	ROL	DATA_H


	LDA DATA_PT
	INC	A
	STA DATA_PT
	CMP	#16
	BEQ	READ_BIT0_200

RREAD_BIT0_100:
	LDA	#1
	STA RETURN_FLAG
	JMP	Q_READ_BIT0

READ_BIT0_200:
	LDA	#0
	STA RETURN_FLAG

	
Q_READ_BIT0:
	RTS
;------------------------------------------------









;---------------------------------------------------
WRITE_CUR_REG:

	
	LDA #8			;
	STA BIT_CNT

WRITE_CUR_REG_40:	

	CLC
	ROL	CUR_REG

	BCC	WRITE_CUR_REG_42

WRITE_CUR_REG_41:			
	JSR	SEND_BIT1
	JMP	WRITE_CUR_REG_50

WRITE_CUR_REG_42:
	JSR	SEND_BIT0
;-----------
WRITE_CUR_REG_50:

	LDA BIT_CNT
	DEC	A
	STA BIT_CNT
	CMP	#0
	BEQ	WRITE_CUR_REG_60
	JMP	WRITE_CUR_REG_40

;----- ----- --------
WRITE_CUR_REG_60:

	LDA !BP0
	AND	#USER_BIT5_INV
	AND	#USER_BIT6_INV
	STA !BP0

;	JSR DELAY
	NOP

Q_WRITE_CUR_REG:
	RTS


;---------------------------------------------------





;------------------------------------------------

SEND_REG80:

	LDA !BP0
	AND	#USER_BIT4_INV		;SET SPI_SS -->LOW
	STA !BP0

	LDA #80					; REG80
	STA CUR_REG


	LDA #8			;
	STA BIT_CNT

SEND_REG80_40:	

	CLC
	ROL	CUR_REG

	BCC	SEND_REG80_42

SEND_REG80_41:			
	JSR	SEND_BIT1
	JMP	SEND_REG80_50

SEND_REG80_42:
	JSR	SEND_BIT0
;-----------
SEND_REG80_50:

	LDA BIT_CNT
	DEC	A
	STA BIT_CNT
	CMP	#0
	BEQ	SEND_REG80_60
	JMP	SEND_REG80_40

;----- ----- --------
SEND_REG80_60:

	
	LDA !BP0
	AND	#USER_BIT6_INV
	STA !BP0

	JSR	DELAY

;	JSR DELAY_1MS


Q_SEND_REG80:
	RTS
;------------------------------------------------

SET_REG82_RX:

;	LDA !BP0
;	AND	#USER_BIT4_INV		;SET SPI_SS -->LOW
;	STA !BP0
;	NOP

	LDA #82
	STA CUR_REG
	LDA #00H
	STA DATA_H
	LDA #80H
	STA DATA_L

	JSR	WRITE_1REG_2DATA_OPERATION

	NOP
Q_SET_REG82_RX:
	RTS


;------------------------------------------------



;-----------------------------------------------------
RX_CONTROL:

;	LDA !BP0
;	AND	#USER_BIT4_INV		;SET SPI_SS -->LOW
;	STA !BP0

	LDA #7
	STA CUR_REG
	LDA #12H
	STA DATA_H

	LDA	#90H		;2.418GHz
	STA DATA_L

	JSR	WRITE_1REG_2DATA_OPERATION

	NOP

Q_RX_CONTROL:
	RTS
;------------------------------------------------

;------------------------------------------------
IDLE_MODE: