main.c

这是msp430f449单片机系统时钟源控制和选择的控制方式源代码

#include <msp430x44x.h>

void ini_sys(void);//申明系统初始化函数
void main(void)
{
    ini_sys();    
}

void ini_sys(void)
{
    //先是看门狗控制
    WDTCTL =WDTPW+WDTHOLD;//看门狗停止
     
    //再是系统时钟控制
    //status register(sr)
    SCFQCTL |=SCFQ_2M+SCFQ_M;   /* fMCLK=64*fACLK *//* Modulation Disable */
    //SCFQCTL |=SCFQ_2M;  /* fMCLK=64*fACLK */
    //#define SCFQ_2M             (0x3F)                     /* fMCLK=64*fACLK */
    //#define SCFQ_M              (0x80)                     /* Modulation Disable */
    
    SCFI0 |=FN_4+FLLD_4;
    //#define FN_4                (0x10)    /* fDCOCLK =   3.2-25Mhz*/
    //#define FN_8                (0x20)    /* fDCOCLK =     5-40Mhz*/
    //#define FLLD0               (0x40)    /* Loop Divider Bit : 0 */
    //#define FLLD1               (0x80)    /* Loop Divider Bit : 1 */
    //#define FLLD_4              (0x80)    /* Multiply Selected Loop Freq. By 4 */
    
    //SCFI1 =THESE bits are modified automatically by the FLL+.
    //
    FLL_CTL0 |=XCAP10PF;
    FLL_CTL0 |=DCOPLUS;
    //FLL_CTL0 &=(~DCOPLUS);
    //#define XCAP10PF            (0x10)                     /* XIN Cap = XOUT Cap = 10pf */
    //#define DCOPLUS             (0x80)                     /* DCO+ Enable */
    
    FLL_CTL1 |=FLL_DIV_1;//设置第一二位
    FLL_CTL1 |=SELS;//设置第三位
    FLL_CTL1 |=SELM_A;  //  设置第四五位
    FLL_CTL1 |=XT2OFF;//设置第六位
    FLL_CTL1 |=SMCLKOFF;//设置第七位
    
    //#define FLL_DIV_1           (0x00)                     /* FLL+ Divide Px.x/ACLK By 1 */
    //#define SELS                (0x04)                     /* Peripheral Module Clock Source (0: DCO, 1: XT2) */
    //#define SELM_DCO            (0x00)                     /* Select DCO for CPU MCLK */
    //#define SELM_XT2            (0x10)                     /* Select XT2 for CPU MCLK */
    //#define SELM_A              (0x18)                     /* Select ACLK (from LFXT1) for CPU MCLK */
    //#define XT2OFF              (0x20)                     /* High Frequency Oscillator 2 (XT2) disable */
    //#define SMCLKOFF            (0x40)                     /* Peripheral Module Clock (SMCLK) disable */
    IE1 =BIT1;//Oscillator fault interrupt enable. This bit enables the OFIFG interrupt.
    //IFG1 =    //Oscillator fault interrupt flag.
}