📄 cstartup.lst
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###############################################################################
# #
# IAR Systems ARM Assembler V4.30A/W32 14/Dec/2005 14:41:43 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
# #
# Source file = D:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IAR\cstartup.s79#
# List file = D:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IAR\binary\List\cstartup.lst#
# Object file = D:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IAR\binary\Obj\cstartup.r79#
# Command line = D:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IAR\cstartup.s79 #
# -OD:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IAR\binary\Obj\ #
# -s+ -M<> -w+ #
# -LD:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IAR\binary\List\ #
# -t8 --cpu ARM7TDMI --fpu None #
# -IC:\Program Files\IAR Systems\Embedded Workbench 4.0 Kickstart\arm\INC\ #
# -ID:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IAR\..\..\Source\portable\IAR\STR71x\ #
# #
###############################################################################
112 00000000
113 00000000
114 00000000 ;-----------------------------------------------
----------------
115 00000000 ; ?CSTARTUP
116 00000000 ;-----------------------------------------------
----------------
117 00000000 MODULE ?CSTARTUP
118 00000000
119 00000000 ; RSEG IRQ_STACK:DATA(2)
120 00000000 ; RSEG SVC_STACK:DATA:NOROOT(2)
121 00000000 ; RSEG CSTACK:DATA(2)
122 00000000 RSEG ICODE:CODE:NOROOT(2)
123 00000000 PUBLIC ?cstartup
124 00000000 EXTERN ?main
125 00000000
126 00000000
127 00000000
128 00000000
129 00000000 CODE32
130 00000000 ?cstartup
131 00000000
132 00000000
133 00000000 0000A0E1 NOP ; Wait for OSC
stabilization
134 00000004 0000A0E1 NOP
135 00000008 0000A0E1 NOP
136 0000000C 0000A0E1 NOP
137 00000010 0000A0E1 NOP
138 00000014 0000A0E1 NOP
139 00000018 0000A0E1 NOP
140 0000001C 0000A0E1 NOP
141 00000020 0000A0E1 NOP
142 00000024
143 00000024
144 00000024 /* Setup a stack for each mode - note
that this only sets up a usable stack
145 00000024 for system/user, SWI and IRQ modes.
Also each mode is setup with
146 00000024 interrupts initially disabled.
*/
147 00000024 DBF021E3 msr CPSR_c, #Mode_UNDEF|I_Bit|F_Bit /*
Undefined Instruction Mode
*/
148 00000028 98D09FE5 LDR SP, =UNDEF_Stack
149 0000002C
150 0000002C D7F021E3 msr CPSR_c, #Mode_ABT|I_Bit|F_Bit /*
Abort Mode */
151 00000030 94D09FE5 LDR SP, =ABT_Stack
152 00000034
153 00000034 D1F021E3 msr CPSR_c, #Mode_FIQ|I_Bit|F_Bit /*
FIQ Mode */
154 00000038 90D09FE5 LDR SP, =FIQ_Stack
155 0000003C
156 0000003C D2F021E3 msr CPSR_c, #Mode_IRQ|I_Bit|F_Bit /* IRQ
Mode */
157 00000040 8CD09FE5 LDR SP, =IRQ_Stack
158 00000044
159 00000044 D3F021E3 msr CPSR_c, #Mode_SVC|I_Bit|F_Bit /*
Supervisor Mode
*/
160 00000048 88D09FE5 LDR SP, =SVC_Stack
161 0000004C
162 0000004C DFF021E3 msr CPSR_c, #Mode_SYS|I_Bit|F_Bit /*
System Mode */
163 00000050 84D09FE5 LDR SP, =USR_Stack
164 00000054
165 00000054 /* We want to start in supervisor mode.
Operation will switch to system
166 00000054 mode when the first task starts.
*/
167 00000054 D3F021E3 msr CPSR_c, #Mode_SVC|I_Bit|F_Bit
168 00000058
169 00000058
170 00000000 IMPORT T0TIMI_Addr
171 00000058
172 00000058 EIC_INIT
173 00000058 80309FE5 LDR r3, =EIC_Base_addr
174 0000005C 0040A0E3 LDR r4, =0x00000000
175 00000060 004083E5 STR r4, [r3, #ICR_off_addr] ;
Disable FIQ and IRQ
176 00000064 204083E5 STR r4, [r3, #IER_off_addr] ;
Disable all channels
interrupts
177 00000068 0040E0E3 LDR r4, =0xFFFFFFFF
178 0000006C 404083E5 STR r4, [r3, #IPR_off_addr] ;
Clear all IRQ pending
bits
179 00000070 0C40A0E3 LDR r4, =0x0C
180 00000074 1C4083E5 STR r4, [r3, #FIR_off_addr] ;
Disable FIQ channels and
clear FIQ pending
bits
181 00000078 0040A0E3 LDR r4, =0x00000000
182 0000007C 084083E5 STR r4, [r3, #CIPR_off_addr] ;
Reset the current priority
register
183 00000080 5C409FE5 LDR r4, =0xE59F0000
184 00000084 184083E5 STR r4, [r3, #IVR_off_addr] ;
Write the LDR pc,pc,#offset
instruction code in
IVR[31:16]
185 00000088 2020A0E3 LDR r2, =32 ; 32
Channel to initialize
186 0000008C 54009FE5 LDR r0, =T0TIMI_Addr ; Read
the address of the IRQs
address table
187 00000090 54109FE5 LDR r1, =0x00000FFF
188 00000094 010000E0 AND r0,r0,r1
189 00000098 6050A0E3 LDR r5, =SIR0_off_addr ; Read
SIR0 address
190 0000009C 084040E2 SUB r4,r0,#8 ;
subtract 8 for prefetch
191 000000A0 48109FE5 LDR r1, =0xF7E8 ; add
the offset to the
0x00000000 address(IVR
address + 7E8 = 0x00000000)
192 000000A4 ;
0xF7E8 used to complete the LDR pc,pc,#offset
opcode
193 000000A4 011084E0 ADD r1,r4,r1 ;
compute the jump offset
194 000000A8 0148A0E1 EIC_INI MOV r4, r1, LSL #16 ; Left
shift the result
195 000000AC 054083E7 STR r4, [r3, r5] ;
Store the result in SIRx
register
196 000000B0 041081E2 ADD r1, r1, #4 ; Next
IRQ address
197 000000B4 045085E2 ADD r5, r5, #4 ; Next
SIR
198 000000B8 012052E2 SUBS r2, r2, #1 ;
Decrement the number of SIR
registers to initialize
199 000000BC F9FFFF1A BNE EIC_INI ; If
more
then
conti
nue
200 000000C0
201 000000C0
202 000000C0 2C009FE5 ldr r0,=?main
203 000000C4 10FF2FE1 bx r0
204 000000C8
205 000000C8 LTORG
205.1 000000C8 TABLE
205.2 000000C8 E8FB0020 Reference on line 148
205.3 000000CC F0FB0020 Reference on line 151
205.4 000000D0 F8FB0020 Reference on line 154
205.5 000000D4 00FE0020 Reference on line 157
205.6 000000D8 00000120 Reference on line 160
205.7 000000DC 00FC0020 Reference on line 163
205.8 000000E0 00F8FFFF Reference on line 173
205.9 000000E4 00009FE5 Reference on line 183
205.10 000000E8 ........ Reference on line 186
205.11 000000EC FF0F0000 Reference on line 187
205.12 000000F0 E8F70000 Reference on line 191
205.13 000000F4 ........ Reference on line 202
205 000000F8 LTORG
206 000000F8
207 000000F8 ENDMOD
##############################
# CRC:1E35 #
# Errors: 0 #
# Warnings: 0 #
# Bytes: 248 #
##############################
##############################
# CRC:1E35 #
# Errors: 0 #
# Warnings: 0 #
# Bytes: 248 #
# Modules: 2 #
# Total errors: 0 #
# Total warnings: 0 #
##############################
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