📄 rccu.lst
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# #
# IAR ARM ANSI C/C++ Compiler V4.30A/W32 KICKSTART 14/Dec/2005 14:41:47 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
# #
# Cpu mode = interwork #
# Endian = little #
# Stack alignment = 4 #
# Source file = D:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IA #
# R\Library\rccu.c #
# Command line = D:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IA #
# R\Library\rccu.c -D _NDEBUG -D STR71X_IAR -lC #
# D:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IA #
# R\binary\List\ --diag_suppress pe191,pa082 -o #
# D:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IA #
# R\binary\Obj\ -s9 --no_clustering --cpu_mode thumb #
# --endian little --cpu ARM7TDMI --stack_align 4 #
# --interwork -e --require_prototypes --fpu None #
# --dlib_config "C:\Program Files\IAR #
# Systems\Embedded Workbench 4.0 #
# Kickstart\arm\LIB\dl4tptinl8n.h" -I #
# D:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IA #
# R\ -I D:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR #
# 71x_IAR\library\include\ -I #
# D:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IA #
# R\..\common\include\ -I D:\board\FreeRTOSV3.2.3\Free #
# RTOS\Demo\ARM7_STR71x_IAR\..\..\source\include\ -I #
# "C:\Program Files\IAR Systems\Embedded Workbench #
# 4.0 Kickstart\arm\INC\" #
# List file = D:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IA #
# R\binary\List\rccu.lst #
# Object file = D:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IA #
# R\binary\Obj\rccu.r79 #
# #
# #
##############################################################################
D:\board\FreeRTOSV3.2.3\FreeRTOS\Demo\ARM7_STR71x_IAR\Library\rccu.c
1 /******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
2 * File Name : rccu.c
3 * Author : MCD Application Team
4 * Date First Issued : 07/28/2003
5 * Description : This file provides all the RCCU software functions
6 ********************************************************************************
7 * History:
8 * 30/11/2004 : V2.0
9 * 14/07/2004 : V1.3
10 * 01/01/2004 : V1.2
11 *******************************************************************************
12 THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
13 CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
14 AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
15 OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
16 OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
17 CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 *******************************************************************************/
19 #include "rccu.h"
20
21 /*******************************************************************************
22 * Function Name : RCCU_PLL1Config
23 * Description : Configures the PLL1 div & mul factors.
24 * Input : New_Mul ( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20,
25 * RCCU_PLL1_Mul_24 )
26 * : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,
27 * RCCU_Div_5, RCCU_Div_6, RCCU_Div_7)
28 * Return : None
29 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
30 void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div )
31 {
\ RCCU_PLL1Config:
\ 00000000 10B4 PUSH {R4}
32 u32 Tmp = ( RCCU->PLL1CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index );
\ 00000002 .... LDR R2,??DataTable7 ;; 0xa0000018
\ 00000004 1368 LDR R3,[R2, #+0]
\ 00000006 3024 MOV R4,#+0x30
\ 00000008 A343 BIC R3,R4
\ 0000000A 0001 LSL R0,R0,#+0x4
\ 0000000C 1843 ORR R0,R3
33 RCCU->PLL1CR = ( Tmp & ~RCCU_DX_Mask ) | New_Div | 0x40;
\ 0000000E 0723 MOV R3,#+0x7
\ 00000010 9843 BIC R0,R3
\ 00000012 0143 ORR R1,R0
\ 00000014 4020 MOV R0,#+0x40
\ 00000016 0843 ORR R0,R1
\ 00000018 1060 STR R0,[R2, #+0]
34 }
\ 0000001A 10BC POP {R4}
\ 0000001C 7047 BX LR ;; return
35
36 /*******************************************************************************
37 * Function Name : RCCU_PLL2Config
38 * Description : Configures the PLL2 div & mul factors.
39 * Input : New_Mul ( RCCU_PLL2_Mul_12, RCCU_PLL2_Mul_16, RCCU_PLL2_Mul_20,
40 * RCCU_Mul_PLL2_28 )
41 * : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,
42 * RCCU_Div_5, RCCU_Div_6, RCCU_Div_7)
43 * Return : None
44 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
45 void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div )
46 {
\ RCCU_PLL2Config:
\ 00000000 10B4 PUSH {R4}
47 u32 Tmp = ( PCU->PLL2CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index );
\ 00000002 .... LDR R2,??DataTable5 ;; 0xa000004c
\ 00000004 1388 LDRH R3,[R2, #+0]
\ 00000006 3024 MOV R4,#+0x30
\ 00000008 A343 BIC R3,R4
\ 0000000A 0001 LSL R0,R0,#+0x4
\ 0000000C 1843 ORR R0,R3
48 PCU->PLL2CR = ( Tmp & ~RCCU_DX_Mask ) | ( New_Div | RCCU_FREEN_Mask );
\ 0000000E 044B LDR R3,??RCCU_PLL2Config_0 ;; 0xfff8
\ 00000010 0340 AND R3,R0
\ 00000012 1943 ORR R1,R3
\ 00000014 8020 MOV R0,#+0x80
\ 00000016 0843 ORR R0,R1
\ 00000018 1080 STRH R0,[R2, #+0]
49 }
\ 0000001A 10BC POP {R4}
\ 0000001C 7047 BX LR ;; return
\ 0000001E C046 NOP
\ ??RCCU_PLL2Config_0:
\ 00000020 F8FF0000 DC32 0xfff8
50
51 /*******************************************************************************
52 * Function Name : RCCU_RCLKSourceConfig
53 * Description : Selects the RCLK source clock
54 * Input : New_Clock ( RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 )
55 * Return : None
56 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
57 void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock )
58 {
\ RCCU_RCLKSourceConfig:
\ 00000000 F0B4 PUSH {R4-R7}
\ 00000002 8721 MOV R1,#+0x87
\ 00000004 C943 MVN R1,R1 ;; #-136
\ 00000006 0422 MOV R2,#+0x4
\ 00000008 D243 MVN R2,R2 ;; #-5
\ 0000000A .... LDR R3,??DataTable7 ;; 0xa0000018
\ 0000000C 0824 MOV R4,#+0x8
\ 0000000E .... LDR R5,??DataTable6 ;; 0xa0000008
\ 00000010 A026 MOV R6,#+0xA0
\ 00000012 3606 LSL R6,R6,#+0x18 ;; #-1610612736
\ 00000014 0028 CMP R0,#+0
\ 00000016 1AD0 BEQ ??RCCU_RCLKSourceConfig_0
\ 00000018 0128 CMP R0,#+0x1
\ 0000001A 14D0 BEQ ??RCCU_RCLKSourceConfig_1
\ 0000001C 0228 CMP R0,#+0x2
\ 0000001E 02D0 BEQ ??RCCU_RCLKSourceConfig_2
\ 00000020 0328 CMP R0,#+0x3
\ 00000022 27D0 BEQ ??RCCU_RCLKSourceConfig_3
\ 00000024 2AE0 B ??RCCU_RCLKSourceConfig_4
59 switch ( New_Clock )
60 {
61 case RCCU_CLOCK2 :{// Resets the CSU_Cksel bit in clk_flag
62 RCCU->CFR &= ~RCCU_CSU_CKSEL_Mask;
\ ??RCCU_RCLKSourceConfig_2:
\ 00000026 2868 LDR R0,[R5, #+0]
\ 00000028 0127 MOV R7,#+0x1
\ 0000002A B843 BIC R0,R7
\ 0000002C 2860 STR R0,[R5, #+0]
63 // Set the CK2_16 Bit in the CFR
64 RCCU->CFR |= RCCU_CK2_16_Mask;
\ 0000002E 2868 LDR R0,[R5, #+0]
\ 00000030 0443 ORR R4,R0
\ 00000032 2C60 STR R4,[R5, #+0]
65 // Deselect The CKAF
66 RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;
\ ??RCCU_RCLKSourceConfig_5:
\ 00000034 3068 LDR R0,[R6, #+0]
\ 00000036 0240 AND R2,R0
\ 00000038 3260 STR R2,[R6, #+0]
67 // switch off the PLL1
68 RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\
69 |0x00000003) & ~RCCU_FREEN_Mask;
\ 0000003A 1868 LDR R0,[R3, #+0]
\ 0000003C 0140 AND R1,R0
\ 0000003E 0320 MOV R0,#+0x3
\ 00000040 0843 ORR R0,R1
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