chip_init.c

TMS320C6713的480*240液晶显示程序

#include "6713.h"
#include "ICETEK-C6713-A.h"

// Functions
void InitInterrupt(void);			// 初始化中断
void init_emif( void );				// 初始化emif接口寄存器
void Delay(unsigned int nTime);		// 延时子程序
void init_pll( void );
void InitCTR();
void disableInterrupt(void);

void InitInterrupt(void)
{
	// 设置中断控制寄存器
	CSR&=0xfffffffe;	// 关中断 GIE=0
	ISTP=0x00000c00;	// 重置中断向量表到0C00h
   	IMH=0x0;			// 指定xint5中断
   	IML=0x0a0;
   	ICR=0xff;			// 清除等待的中断
	IER=0x23;			// 使能xint5中断
	CSR=CSR|1; 			// 开中断
}

void disableInterrupt(void)
{	
	IER=0;	
}
void audioinit_MCBSP0(void)
{
//init MCBSP0 
    McBSP0_SPCR =0;             
    McBSP0_RCR =0x00140;        
    McBSP0_XCR =0x00140;     
    McBSP0_PCR = 0x03;          
    McBSP0_SRGR = 0x20000001;     
    McBSP0_SPCR=0x00c50001;     
}

void audioinit_MCBSP1(void)
{
//init MCBSP1 
    McBSP1_SPCR = 0;               
    McBSP1_RCR  = 0x00040;            
    McBSP1_XCR  = 0x10040;            
    McBSP1_SRGR = 0x20001363;     
    McBSP1_PCR  = 0xa0a;         
    McBSP1_SPCR = 0xC31000;
   
    
}
void audiochip_sel( void )
{
   DEVCFG = 0x0;

}

void  init_pll( void )
{
    *(int *)PLL_CSR  &= ~CSR_PLLEN;
    *(int *)PLL_CSR  |= CSR_PLLRST;
    *(int *)PLL_DIV0    = DIV_ENABLE + 0;  
    *(int *)PLL_MULT    = 1;               
    *(int *)PLL_OSCDIV1 = DIV_ENABLE + 4;
    *(int *)PLL_DIV3    = DIV_ENABLE + 3; 
    *(int *)PLL_DIV2    = DIV_ENABLE + 3; 
    *(int *)PLL_DIV1    = DIV_ENABLE + 1; 
    *(int *)PLL_CSR  &= ~CSR_PLLRST;
    *(int *)PLL_CSR |= CSR_PLLEN;

}

void Delay(unsigned int nDelay)
{
	int ii,jj,kk=0;
	for ( ii=0;ii<nDelay;ii++ )
	{
		for ( jj=0;jj<1024;jj++ )
		{
			kk++;
		}
	}
}

void InitCTR()
{
    CTRSTATUS=0x80;	
    CTRSTATUS=0x0;
    CTRSTATUS=0x80;
    CTRSTATUS=0x0;
	CTRCLKEY=0;
	CTRLED=0xff;
}

void init_emif()
{
	#define EMIF_GCTL       0x01800000
	#define EMIF_CE1        0x01800004
	#define EMIF_CE0        0x01800008
	#define EMIF_CE2        0x01800010
	#define EMIF_CE3        0x01800014
	#define EMIF_SDRAMCTL   0x01800018
	#define EMIF_SDRAMTIM   0x0180001C
	#define EMIF_SDRAMEXT   0x01800020
	#define EMIF_CCFG       0x01840000;  /* Cache configuration register */
	
	/* EMIF setup */
	*(int *)EMIF_GCTL     = 0x00000078;
	*(int *)EMIF_CE0      = 0xffffbf93;  /* CE0 SDRAM                     */
	*(int *)EMIF_CE1      = 0xffffff13;  /* CE1 Flash 16-bit               */
	*(int *)EMIF_CE2      = 0xffffff23;  /* CE2 Daughtercard 32-bit async */
	*(int *)EMIF_CE3      = 0xffffff23;  /* CE3 Daughtercard 32-bit async */
	*(int *)EMIF_SDRAMCTL = 0x53115000;  /* SDRAM control                 */
	*(int *)EMIF_SDRAMTIM = 0x00000578;  /* SDRAM timing (refresh)        */
	*(int *)EMIF_SDRAMEXT = 0x000a8529;  /* SDRAM Extension register      */
}