📄 board.lis
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0008 ; 0x2E, //*0x2E IOCFG1 GDO1 output pin configuration.
0008 ; 0x2E, //*0x0C IOCFG0 GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
0008 ; 0x07, // FIFOTHR RX FIFO and TX FIFO thresholds
0008 ; 0xD3, // SYNC1 Sync word, high byte
0008 ; 0x91, // SYNC0 Sync word, low byte
0008 ; 0xFF, // PKTLEN Packet length.
0008 ; 0x04, //*0x00 PKTCTRL1 Packet automation control.
0008 ; 0x45, //*0x12 PKTCTRL0 Packet automation control.
0008 ; 0x00, // ADDR Device address.
0008 ; 0x00, // CHANNR Channel number.
0008 ; 0x06,//0x0C, //*0x06 FSCTRL1 Frequency synthesizer control.
0008 ; 0x00, // FSCTRL0 Frequency synthesizer control.
0008 ; #ifdef RF_429
0008 ; 0x10, // FREQ2 Frequency control word, high byte.
0008 ; 0x80, // FREQ1 Frequency control word, middle byte.
0008 ; 0x83, // FREQ0 Frequency control word, low byte.
0008 ; #endif
0008 ;
0008 ; #ifdef RF_433
0008 ; 0x10, // FREQ2 Frequency control word, high byte.
0008 ; 0xA7, // FREQ1 Frequency control word, middle byte.
0008 ; 0x62, // FREQ0 Frequency control word, low byte.
0008 ; #endif
0008 ; #ifdef RF_461
0008 ; 0x11, // FREQ2 Frequency control word, high byte.
0008 ; 0xBB, // FREQ1 Frequency control word, middle byte.
0008 ; 0x13, // FREQ0 Frequency control word, low byte.
0008 ; #endif
0008 ; 0xF5, // MDMCFG4 Modem configuration.
0008 ; 0x83, // MDMCFG3 Modem configuration.
0008 ; 0x03, //*0x00 MDMCFG2 Modem configuration.
0008 ; 0x22, // MDMCFG1 Modem configuration.
0008 ; 0xF8, // MDMCFG0 Modem configuration.
0008 ; 0x15, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0008 ; 0x0E, //*0x07 MCSM2 Main Radio Control State Machine configuration.
0008 ; 0x30, // MCSM1 Main Radio Control State Machine configuration.
0008 ; 0x18, // MCSM0 Main Radio Control State Machine configuration.
0008 ; 0x16,//0x15, //*0x16 FOCCFG Frequency Offset Compensation Configuration.
0008 ; 0x6C, // BSCFG Bit synchronization Configuration.
0008 ; 0x03, // AGCCTRL2 AGC control.
0008 ; 0x40, // AGCCTRL1 AGC control.
0008 ; 0x91, // AGCCTRL0 AGC control.
0008 ; 0x87, // WOREVT1 0x1E //定义EVENT0时间
0008 ; 0x6B, // WOREVT0 0x1F //...
0008 ; 0xF8, // WORCTRL 0x20 //关闭RC，定义EVENT1时间
0008 ; 0x56, // FREND1 Front end RX configuration.
0008 ; 0x10, // FREND0 Front end RX configuration.
0008 ; 0xE9,//0xA9, //*0xE9 FSCAL3 Frequency synthesizer calibration.
0008 ; 0x2A,//0x2A, //*0x2A FSCAL2 Frequency synthesizer calibration.
0008 ; 0x00,//0x0D, //*0x00 FSCAL1 Frequency synthesizer calibration.
0008 ; 0x1F,//0x11, //*0x1F FSCAL0 Frequency synthesizer calibration.
0008 ; };
0008 ; #endif
0008 ; INT8U RFState; //保存射频状态，共两种状态：发送、接收状态
0008 ;
0008 ;
0008 ; INT8U CC1100IntHFlg; //CC1100产生高电平中断标志
0008 ; INT8U CC1100IntLFlg;
0008 ;
0008 ; /*
0008 ; ************************************************************
0008 ; *Description:RF收发中断处理函数
0008 ; *Arguments :none
0008 ; *Returns :none
0008 ; *Notes :
0008 ; ************************************************************
0008 ; */
0008 ; #pragma interrupt_handler IntPCINT2:iv_PCINT2
0008 ; void IntPCINT2 (void)
0008 ; {
0008 .dbline 175
0008 ; if (GDO2_STATE != 0x00)
0008 4A9B sbis 0x9,2
000A 07C0 rjmp L2
000C .dbline 176
000C ; {
000C .dbline 177
000C ; CC1100IntHFlg = TRUE; //上升沿中断，等待下降沿中断
000C 81E0 ldi R24,1
000E 8093BE00 sts _CC1100IntHFlg,R24
0012 .dbline 178
0012 ; if(RFSend_Start==TRUE)
0012 8091BF00 lds R24,_RFSend_Start
0016 8130 cpi R24,1
0018 01F4 brne L4
001A .dbline 179
001A ; {
001A .dbline 182
001A ; //TXEN_SET_L;//打开功率放大
001A ; //RXEN_SET_L;//打开功率放大
001A ; }
001A L4:
001A .dbline 183
001A ; }
001A L2:
001A .dbline 184
001A ; if ((CC1100IntHFlg == TRUE) && (GDO2_STATE == 0x00))
001A 8091BE00 lds R24,_CC1100IntHFlg
001E 8130 cpi R24,1
0020 71F4 brne L6
0022 4A99 sbic 0x9,2
0024 0CC0 rjmp L6
0026 .dbline 185
0026 ; {
0026 .dbline 186
0026 ; CC1100IntHFlg = FALSE; //下降沿中断
0026 2224 clr R2
0028 2092BE00 sts _CC1100IntHFlg,R2
002C .dbline 187
002C ; CC1100IntLFlg = TRUE;
002C 81E0 ldi R24,1
002E 8093BD00 sts _CC1100IntLFlg,R24
0032 .dbline 189
0032 ;
0032 ; if(RFSend_Start==TRUE)
0032 8091BF00 lds R24,_RFSend_Start
0036 8130 cpi R24,1
0038 11F4 brne L8
003A .dbline 190
003A ; {
003A .dbline 193
003A ; //TXEN_SET_H;//关闭功率放大
003A ; //RXEN_SET_H;//关闭功率放大
003A ; RFSend_Start=FALSE;
003A 2092BF00 sts _RFSend_Start,R2
003E .dbline 194
003E ; }
003E L8:
003E .dbline 195
003E L6:
003E .dbline -2
003E L1:
003E 2990 ld R2,y+
0040 2FBE out 0x3f,R2
0042 8991 ld R24,y+
0044 2990 ld R2,y+
0046 .dbline 0 ; func end
0046 1895 reti
0048 .dbend
0048 .dbfunc e port_init _port_init fV
.even
0048 _port_init::
0048 .dbline -1
0048 .dbline 206
0048 ; }
0048 ; }
0048 ; /*
0048 ; ************************************************************
0048 ; *Description:初始化IO端口
0048 ; *Arguments :none
0048 ; *Returns :none
0048 ; *Notes :
0048 ; ************************************************************
0048 ; */
0048 ; void port_init(void)
0048 ; {
0048 .dbline 207
0048 ; DDRB =0x00;
0048 2224 clr R2
004A 24B8 out 0x4,R2
004C .dbline 208
004C ; PORTB=0x3F;
004C 8FE3 ldi R24,63
004E 85B9 out 0x5,R24
0050 .dbline 210
0050 ;
0050 ; DDRD =0x08;//PD3 KEY
0050 88E0 ldi R24,8
0052 8AB9 out 0xa,R24
0054 .dbline 211
0054 ; PORTD=0xD0;
0054 80ED ldi R24,208
0056 8BB9 out 0xb,R24
0058 .dbline 213
0058 ;
0058 ; BEEP_INIT();
0058 559A sbi 0xa,5
005A .dbline 214
005A ; BEEP_OFF();
005A 5D98 cbi 0xb,5
005C .dbline -2
005C L10:
005C .dbline 0 ; func end
005C 0895 ret
005E .dbend
005E .dbfunc e uart0_init _uart0_init fV
.even
005E _uart0_init::
005E .dbline -1
005E .dbline 230
005E ;
005E ; //TXEN_OUT;
005E ; //TXEN_SET_H;
005E ; //RXEN_OUT;
005E ; //RXEN_SET_H;
005E ; }
005E ; /*
005E ; ************************************************************
005E ; *Description:初始化串口
005E ; *Arguments :none
005E ; *Returns :none
005E ; *Notes :
005E ; ************************************************************
005E ; */
005E ; void uart0_init(void)
005E ; {
005E .dbline 231
005E ; UBRR0H = Sys_Set[Baud_Set_Num].ubrr0h_val;
005E 20900100 lds R2,_Baud_Set_Num
0062 88E0 ldi R24,8
0064 829D mul R24,R2
0066 F001 movw R30,R0
0068 80E0 ldi R24,<_Sys_Set+2
006A 90E0 ldi R25,>_Sys_Set+2
006C E80F add R30,R24
006E F91F adc R31,R25
0070 E491 lpm R30,Z
0072 E093C500 sts 197,R30
0076 .dbline 232
0076 ; UBRR0L = Sys_Set[Baud_Set_Num].ubrr0l_val;
0076 88E0 ldi R24,8
0078 829D mul R24,R2
007A F001 movw R30,R0
007C 80E0 ldi R24,<_Sys_Set+1
007E 90E0 ldi R25,>_Sys_Set+1
0080 E80F add R30,R24
0082 F91F adc R31,R25
0084 E491 lpm R30,Z
0086 E093C400 sts 196,R30
008A .dbline 234
008A ;
008A ; UCSR0C = BIT(UCSZ01) | BIT(UCSZ00); //Set frame format: 8data, 1stop bit, asyn mode
008A 86E0 ldi R24,6
008C 8093C200 sts 194,R24
0090 .dbline 235
0090 ; UCSR0B = BIT(RXEN0) | BIT(TXEN0); //使能串口发送、接收
0090 88E1 ldi R24,24
0092 8093C100 sts 193,R24
0096 .dbline 236
0096 ; EN_RX_INT();
0096 8091C100 lds R24,193
009A 8068 ori R24,128
009C 8093C100 sts 193,R24
00A0 .dbline -2
00A0 L11:
00A0 .dbline 0 ; func end
00A0 0895 ret
00A2 .dbend
.area vector(rom, abs)
.org 38
0026 51C0 rjmp _uart0_tx_isr
.area text(rom, con, rel)
00A2 .dbfile D:\WIRELE~1\CC1020~1\SoftWare\SoftWare\board.c
00A2 .dbfunc e uart0_tx_isr _uart0_tx_isr fV
.even
00A2 _uart0_tx_isr::
00A2 2A92 st -y,R2
00A4 8A93 st -y,R24
00A6 9A93 st -y,R25
00A8 EA93 st -y,R30
00AA FA93 st -y,R31
00AC 2FB6 in R2,0x3f
00AE 2A92 st -y,R2
00B0 .dbline -1
00B0 .dbline 248
00B0 .dbline 249
00B0 80E0 ldi R24,<_RFReceive_Buf
00B2 90E0 ldi R25,>_RFReceive_Buf
00B4 E0910B00 lds R30,_RFReceiveCnt
00B8 FF27 clr R31
00BA E80F add R30,R24
00BC F91F adc R31,R25
00BE 2080 ldd R2,z+0
00C0 2092C600 sts 198,R2
00C4 .dbline 250
00C4 80910B00 lds R24,_RFReceiveCnt
00C8 8F5F subi R24,255 ; addi 1
00CA 80930B00 sts _RFReceiveCnt,R24
00CE .dbline 251
00CE 20900A00 lds R2,_RFReceiveLen
00D2 8215 cp R24,R2
00D4 29F4 brne L15
00D6 .dbline 252
00D6 .dbline 253
00D6 8091C100 lds R24,193
00DA 8F7D andi R24,223
00DC 8093C100 sts 193,R24
00E0 .dbline 254
00E0 L15:
00E0 .dbline -2
00E0 L14:
00E0 2990 ld R2,y+
00E2 2FBE out 0x3f,R2
00E4 F991 ld R31,y+
00E6 E991 ld R30,y+
00E8 9991 ld R25,y+
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