ppctrap.s

可用于嵌入式编程学习

    ///stw     r4, TcxContextFlags(r11)// mark as partial context
    b      Reschedule

    DUMMY_EXIT(xKCall)


// CaptureContext is invoked in kernel context on the user thread's stack to
// build a context structure to be used for exception unwinding.
//
//  (r1) = aligned stack pointer

	SPECIAL_ENTRY(CaptureContext)


    stwu    r1, -ContextFrameLength-StackFrameHeaderLength(r1)
    stw     r0, CxGpr0+StackFrameHeaderLength(r1)
	// CxGpr1 is filled by ExceptionDispatch.  The unwinder
	// will recover that value from this (otherwise useless)
	// prolog instruction
	stw		r1, CxGpr1+StackFrameHeaderLength(r1)
    stw     r2, CxGpr2+StackFrameHeaderLength(r1)
    stw     r3, CxGpr3+StackFrameHeaderLength(r1)
    stw     r4, CxGpr4+StackFrameHeaderLength(r1)
    stw     r5, CxGpr5+StackFrameHeaderLength(r1)
    stw     r6, CxGpr6+StackFrameHeaderLength(r1)
    stw     r7, CxGpr7+StackFrameHeaderLength(r1)
    stw     r8, CxGpr8+StackFrameHeaderLength(r1)
    stw     r9, CxGpr9+StackFrameHeaderLength(r1)
    stw     r10, CxGpr10+StackFrameHeaderLength(r1)
    stw     r11, CxGpr11+StackFrameHeaderLength(r1)
    stw     r12, CxGpr12+StackFrameHeaderLength(r1)
    stw     r13, CxGpr13+StackFrameHeaderLength(r1)
    stw     r14, CxGpr14+StackFrameHeaderLength(r1)
    stw     r15, CxGpr15+StackFrameHeaderLength(r1)
    stw     r16, CxGpr16+StackFrameHeaderLength(r1)
    stw     r17, CxGpr17+StackFrameHeaderLength(r1)
    stw     r18, CxGpr18+StackFrameHeaderLength(r1)
    stw     r19, CxGpr19+StackFrameHeaderLength(r1)
    stw     r20, CxGpr20+StackFrameHeaderLength(r1)
    stw     r21, CxGpr21+StackFrameHeaderLength(r1)
    stw     r22, CxGpr22+StackFrameHeaderLength(r1)
    stw     r23, CxGpr23+StackFrameHeaderLength(r1)
    stw     r24, CxGpr24+StackFrameHeaderLength(r1)
    stw     r25, CxGpr25+StackFrameHeaderLength(r1)
    stw     r26, CxGpr26+StackFrameHeaderLength(r1)
    stw     r27, CxGpr27+StackFrameHeaderLength(r1)
    stw     r28, CxGpr28+StackFrameHeaderLength(r1)
    stw     r29, CxGpr29+StackFrameHeaderLength(r1)
    stw     r30, CxGpr30+StackFrameHeaderLength(r1)
    stw     r31, CxGpr31+StackFrameHeaderLength(r1)
    mfcr    r0
    stw     r0, CxCr+StackFrameHeaderLength(r1)
    mfxer   r0
    stw     r0, CxXer+StackFrameHeaderLength(r1)
    mfspr   r0, SRR1
    stw     r0, CxMsr+StackFrameHeaderLength(r1)


    // removed because CxIar is fixed up (and restored) by
    // ExceptionDispatch

    // mfspr    r0, SRR0
    // stw      r0, CxIar+StackFrameHeaderLength(r1)


    mflr    r0
    stw     r0, CxLr+StackFrameHeaderLength(r1)

    // ExceptionDispatch will fix up the CxIar value so that during a
    // nested RaiseException we are able to unwind correctly through
    // capture context. The unwinder only restores the LR the first
    // time it reaches a mflr instruction, the mflr above
    // will be ignored during unwind.
    //
    // JWM

    mflr    r0
    stw     r0, CxIar+StackFrameHeaderLength(r1)


    mfctr   r0
    stw     r0, CxCtr+StackFrameHeaderLength(r1)
    PROLOGUE_END(CaptureContext)
    li      r0, CONTEXT_CONTROL | CONTEXT_INTEGER
    stw     r0, CxContextFlags+StackFrameHeaderLength(r1)
    lwz     r2, NKGp(0)                     // (r2) = kernel's Global pointer
    addi    r3, r1, StackFrameHeaderLength  // (r3) = ptr to ContextRecord
    bl      ExceptionDispatch

// Reload possibly edited context from the ContextRecord.
    lwz     r0, CxGpr0+StackFrameHeaderLength(r1)
    lwz     r2, CxGpr2+StackFrameHeaderLength(r1)
    lwz     r5, CxGpr5+StackFrameHeaderLength(r1)
    lwz     r6, CxGpr6+StackFrameHeaderLength(r1)
    lwz     r7, CxGpr7+StackFrameHeaderLength(r1)
    lwz     r8, CxGpr8+StackFrameHeaderLength(r1)
    lwz     r9, CxGpr9+StackFrameHeaderLength(r1)
    lwz     r10, CxGpr10+StackFrameHeaderLength(r1)
    lwz     r11, CxGpr11+StackFrameHeaderLength(r1)
    lwz     r12, CxGpr12+StackFrameHeaderLength(r1)
    lwz     r13, CxGpr13+StackFrameHeaderLength(r1)
    lwz     r14, CxGpr14+StackFrameHeaderLength(r1)
    lwz     r15, CxGpr15+StackFrameHeaderLength(r1)
    lwz     r16, CxGpr16+StackFrameHeaderLength(r1)
    lwz     r17, CxGpr17+StackFrameHeaderLength(r1)
    lwz     r18, CxGpr18+StackFrameHeaderLength(r1)
    lwz     r19, CxGpr19+StackFrameHeaderLength(r1)
    lwz     r20, CxGpr20+StackFrameHeaderLength(r1)
    lwz     r21, CxGpr21+StackFrameHeaderLength(r1)
    lwz     r22, CxGpr22+StackFrameHeaderLength(r1)
    lwz     r23, CxGpr23+StackFrameHeaderLength(r1)
    lwz     r24, CxGpr24+StackFrameHeaderLength(r1)
    lwz     r25, CxGpr25+StackFrameHeaderLength(r1)
    lwz     r26, CxGpr26+StackFrameHeaderLength(r1)
    lwz     r27, CxGpr27+StackFrameHeaderLength(r1)
    lwz     r28, CxGpr28+StackFrameHeaderLength(r1)
    lwz     r29, CxGpr29+StackFrameHeaderLength(r1)
    lwz     r30, CxGpr30+StackFrameHeaderLength(r1)
    lwz     r31, CxGpr31+StackFrameHeaderLength(r1)

    lwz     r3, CxCr+StackFrameHeaderLength(r1)
    lwz     r4, CxXer+StackFrameHeaderLength(r1)
    mtcrf   0xff, r3
    mtxer   r4
    lwz     r3, CxLr+StackFrameHeaderLength(r1)
    lwz     r4, CxCtr+StackFrameHeaderLength(r1)
    mtlr    r3
    mtctr   r4

    mfmsr   r3
    MSR_CLR_EE(r3)
    mtmsr   r3                  // disable interrupts before mucking w/SRRx

    //
    //  "prime" the TB/Cache by prefetching r1, r3, and r4. No TB miss can
    //  be allowed to occur after SRR0 and SRR1 get updated:
    //

    lwz     r3, CxGpr3+StackFrameHeaderLength(r1)
    lwz     r4, CxGpr4+StackFrameHeaderLength(r1)
    lwz     r3, CxGpr1+StackFrameHeaderLength(r1)

    lwz     r3, CxMsr+StackFrameHeaderLength(r1)
    lwz     r4, CxIar+StackFrameHeaderLength(r1)
    mtspr   SRR1, r3
    mtspr   SRR0, r4

    //
    //  No exceptions (including TB misses) may occur before the rfi:
    //

    lwz     r3, CxGpr3+StackFrameHeaderLength(r1)
    lwz     r4, CxGpr4+StackFrameHeaderLength(r1)
    lwz     r1, CxGpr1+StackFrameHeaderLength(r1)
    rfi
    DUMMY_EXIT(CaptureContext)



//
// HwInterruptVector - Hardware interrupt vector
//
// This is the handler for incoming hw interrupts.  This code will be copied to
// the HW interrupt vector
//

HwInterruptHandler:

    mtspr   SPRG1, r14
    mtspr   SPRG2, r5

    lis     r5, [hia]OEMInterruptHandler
    addi    r5, r5, [lo]OEMInterruptHandler

    ba      KPageHwInterruptHandler


.set    HwInterruptHandlerLen, $ - HwInterruptHandler

//
// DecrementerHandler - Decrementer Interrupt Vector
//
// This is the handler for incoming decrmenter interrupts.  This code will be copied
// to the decrementer interrupt vector
//

DecrementerHandler:

    mtspr   SPRG1, r14
    mtspr   SPRG2, r5

    lis     r5, [hia]OEMDecrementer
    addi    r5, r5, [lo]OEMDecrementer

    ba      KPageHwInterruptHandler

.set    DecrementerHandlerLen, $ - DecrementerHandler



//
// GeneralHandler - general interrupt handling code
//
//  This code is copied into each 256 byte vector location in low
// memory. The "li r4,0" is adjusted to be (vector address)/256.
//

GeneralHandler:
    mtspr   SPRG1, r4
    mtspr   SPRG2, r5
    li      r4, 0
    mfspr   r5, DAR
    ba      KPageGeneralHandler
    .set GeneralHandlerLen, $ - GeneralHandler

    .globl  NullSection
NullSection0:
    .long   KPageBlock
NullSection:
    .space  (BLOCK_MASK+1)*4

//
//  Copy Table:
//  This table specifies the special interrupt handlers and KPage handler
//  addresses which need to be copied into low memory and the KPage. The
//  format of each entry is (Dest, Src, Length). All bytes from <Start> to
//  <End> are copied into the location <Dest>.  The Src Address is specified
//  as the offset from label KSRefPoint.
//

CopyTable:
    .long   ITBMissVector,  ITBMiss-KSRefPoint, 0x100
    .long   DTBMissVector,  DTBMiss-KSRefPoint, 0x100
    .long   ITBErrorVector, ITBError-KSRefPoint, 0x100
    .long   DTBErrorVector, DTBError-KSRefPoint, 0x100
    .long   HwInterruptVector, HwInterruptHandler-KSRefPoint, HwInterruptHandlerLen
    .long   DecrementerVector, DecrementerHandler-KSRefPoint, DecrementerHandlerLen
    .long   LowHandlers,    KPageHandlers-KSRefPoint
    .long       KPageHandlers.End - KPageHandlers
#if PPC403
    .long   ClockIntVector, ClockHandler-KSRefPoint
    .long       ClockHandlerEnd - ClockHandler
#endif
    .long   -1  // end of table

    .align  2

    LEAF_ENTRY(KernelStart)
//
// KernelStart - kernel initial startup code
//
// Branch here from the boot vector code after the minimum OEM h/w
// initialization has been completed. At this point:
//  CPU in PowerPC Little-Endian mode.
//  interrupts are disabled
//  relocation is disabled
//  the cache is disabled
//  RAM & ROM accesses are allowed and RAM refresh is working
//  No interrupt vectors have been installed.
//
// The kernel will initialize the interrupt handlers in low memory, setup the kernel
// data page, enable internal interrupts (TLB misses, etc), enable relocation,
// call OEMInit() to finish OEM h/w init, enable external interrupts, init the
// kernel memory system and scheduler and jump to the scheduler to run the initial
// thread.
//
//  Entry   (r3) = address of the a physical to virtual table (if applicable)
//
//  Exit    never returns
//


//
// Set up Reference pointer. Used for accesssing data within this module.
//

    bl KSRefPoint

KSRefPoint:
    mflr    r31

//
// Zero out the kernel data page.
//
// (r31) = Address of KSRefPoint
//

    li      r30, KPAGE_BASE - 4             // Get the start of the KPAGE-4
    li      r29, KData_size - KPAGE_BASE    // Calculate length of KPAGE
    srwi    r29, r29, 2                     // copying by words
    mtctr   r29                             // Load length into ctr
    li      r28, 0                          // zero r28
ZeroKPageLoop:
    stwu    r28, 4(r30)                     // Zero KPAGE
    bdnz    ZeroKPageLoop

//
// Copy default interrupt handlers to low memory.
//
// (r31) = Address of KSRefPoint
//

    addi    r30, r31, GeneralHandler - KSRefPoint // (r30) = ptr to GeneralHandler

    lwz     r29, 0x00(r30)  // (r3) = "mtspr SPRG1, r4"
    lwz     r28, 0x04(r30)  // (r4) = "mtspr SPRG2, r5"
    lwz     r27, 0x08(r30)  // (r5) = "li r4, 0"
    lwz     r26, 0x0c(r30)  // (r6) = "mfspr r5, DAR"
    lwz     r25, 0x10(r30)  // (r7) = "ba KPageGeneralHandler"
    li      r30, -0x100
ks16:
    stwu    r29, 0x100(r30)
    stw     r28, 4(r30)
    stw     r27, 8(r30)
    stw     r26, 12(r30)
    stw     r25, 16(r30)
    cmplwi  r30, 0x3000
    addi    r27, r27, 1     // (r27) = "li r4, N"
    blt+    ks16


//
// Copy special interrupt handlers and KPage code to low memory.
//
// (r31) = Address of KSRefPoint
//

    addi    r30, r31, CopyTable - KSRefPoint// r30 = ptr to CopyTable
    addi    r30, r30, -12                   // start at -12 from table start

InitLoop:
    lwzu    r29, 12(r30)                    // (r29) = destination address
    cmpwi   r29, -1
    beq-    CopyDone                        // done copying

    lwz     r28, 4(r30)                     // (r28) = src addr -KSRefPoint
    add     r28, r31, r28                   // (r28) = src address
    lwz     r27, 8(r30)                     // (r27) = length

    srwi    r27, r27, 2                     // Copy word chunks
    mtctr   r27                             // load length to CTR

    addi    r29, r29, -4                    // Back off dest and source
    addi    r28, r28, -4                    //  pointers by 1 word for copy

CopyLoop:
    lwzu    r26, 4(r28)                     // Perform copy with pointer
    stwu    r26, 4(r29)                     //  index updates
    bdnz    CopyLoop

    b       InitLoop                        // Next table entry

CopyDone:

//
// Store the HandleBase into the KPAGE
//

    lis     r30, 0x8000
    stw     r30, HandleBase(0)

//
// Fill in virtual memory array: All entries point to NullSection by default.
//

    lis     r30, [hia]NullSection0          // Get pointer to NullSection
    addi    r30, r30, [lo]NullSection0
    li      r29, SectionTable-4

    stwu    r30, 4(r29)                     // Section zero -> KPage Block
    addi    r30, r30, 4                     // Other sections -> NULL_BLOCK

    li      r28, 64-1                       // Initialize remaining sections
    mtctr   r28
ks14:
    stwu    r30, 4(r29)
    bdnz    ks14

//