📄 ad9852.lst
字号:
__start:
__text_start:
002D E5CF LDI R28,0x5F
002E E0D4 LDI R29,4
002F BFCD OUT 0x3D,R28
0030 BFDE OUT 0x3E,R29
0031 51C0 SUBI R28,0x10
0032 40D0 SBCI R29,0
0033 EA0A LDI R16,0xAA
0034 8308 STD Y+0,R16
0035 2400 CLR R0
0036 E6E6 LDI R30,0x66
0037 E0F0 LDI R31,0
0038 E010 LDI R17,0
0039 36E6 CPI R30,0x66
003A 07F1 CPC R31,R17
003B F011 BEQ 0x003E
003C 9201 ST R0,Z+
003D CFFB RJMP 0x0039
003E 8300 STD Z+0,R16
003F E5E4 LDI R30,0x54
0040 E0F0 LDI R31,0
0041 E6A0 LDI R26,0x60
0042 E0B0 LDI R27,0
0043 E010 LDI R17,0
0044 35EA CPI R30,0x5A
0045 07F1 CPC R31,R17
0046 F021 BEQ 0x004B
0047 95C8 LPM
0048 9631 ADIW R30,1
0049 920D ST R0,X+
004A CFF9 RJMP 0x0044
004B 940E00B5 CALL _main
_exit:
004D CFFF RJMP _exit
_AD9852_ByteSend:
i --> R20
dat --> R16
004E 940E00FF CALL push_gset1
FILE: D:\RJ\Project\AVR\AD9852\AD9852.h
(0001) #ifndef _AD9852_H_
(0002) #define _AD9852_H_
(0003) #include <iom16v.h>
(0004)
(0005) #define AD9852_CTRL_DDR DDRB
(0006) #define AD9852_CTRL_PORT PORTB
(0007) #define AD9852_CTRL_PIN PINB
(0008)
(0009) #define AD9852_MasterReset 0
(0010) #define AD9852_CLKPOWER 2
(0011) #define AD9852_IORESET 5
(0012) #define AD9852_SCLK 3
(0013) #define AD9852_SDIO 6
(0014) #define AD9852_IOUD 7
(0015)
(0016) #define AD9852_Set_MasterReset() AD9852_CTRL_DDR |= (0x01<<AD9852_MasterReset); AD9852_CTRL_PORT |= (0x01<<AD9852_MasterReset)
(0017) #define AD9852_Clr_MasterReset() AD9852_CTRL_DDR |= (0x01<<AD9852_MasterReset); AD9852_CTRL_PORT &= (~(0x01<<AD9852_MasterReset))
(0018)
(0019) #define AD9852_Set_CLKPOWER() AD9852_CTRL_DDR |= (0x01<<AD9852_CLKPOWER); AD9852_CTRL_PORT |= (0x01<<AD9852_CLKPOWER)
(0020) #define AD9852_Clr_CLKPOWER() AD9852_CTRL_DDR |= (0x01<<AD9852_CLKPOWER); AD9852_CTRL_PORT &= (~(0x01<<AD9852_CLKPOWER))
(0021)
(0022) #define AD9852_Set_IORESET() AD9852_CTRL_DDR |= (0x01<<AD9852_IORESET); AD9852_CTRL_PORT |= (0x01<<AD9852_IORESET)
(0023) #define AD9852_Clr_IORESET() AD9852_CTRL_DDR |= (0x01<<AD9852_IORESET); AD9852_CTRL_PORT &= (~(0x01<<AD9852_IORESET))
(0024)
(0025) #define AD9852_Set_SCLK() AD9852_CTRL_DDR |= (0x01<<AD9852_SCLK); AD9852_CTRL_PORT |= (0x01<<AD9852_SCLK)
(0026) #define AD9852_Clr_SCLK() AD9852_CTRL_DDR |= (0x01<<AD9852_SCLK); AD9852_CTRL_PORT &= (~(0x01<<AD9852_SCLK))
(0027)
(0028) #define AD9852_Set_SDIO() AD9852_CTRL_DDR |= (0x01<<AD9852_SDIO); AD9852_CTRL_PORT |= (0x01<<AD9852_SDIO)
(0029) #define AD9852_Clr_SDIO() AD9852_CTRL_DDR |= (0x01<<AD9852_SDIO); AD9852_CTRL_PORT &= (~(0x01<<AD9852_SDIO))
(0030)
(0031) #define AD9852_Set_IOUD() AD9852_CTRL_DDR |= (0x01<<AD9852_IOUD); AD9852_CTRL_PORT |= (0x01<<AD9852_IOUD)
(0032) #define AD9852_Clr_IOUD() AD9852_CTRL_DDR |= (0x01<<AD9852_IOUD); AD9852_CTRL_PORT &= (~(0x01<<AD9852_IOUD))
(0033)
(0034) void AD9852_DataPost(unsigned char Addr, unsigned char *pDat, unsigned char Len);
(0035)
(0036) void AD9852_ByteSend(unsigned char dat)
(0037) {
(0038) unsigned char i;
(0039) for (i=0;i<8;i++)
0050 2744 CLR R20
0051 C00F RJMP 0x0061
(0040) {
(0041) AD9852_Clr_SCLK();
0052 9ABB SBI 0x17,3
0053 98C3 CBI 0x18,3
(0042) asm("nop");
0054 0000 NOP
(0043) if ( dat & 0x80 )
0055 FF07 SBRS R16,7
0056 C003 RJMP 0x005A
(0044) {
(0045) AD9852_Set_SDIO();
0057 9ABE SBI 0x17,6
0058 9AC6 SBI 0x18,6
(0046) }
0059 C002 RJMP 0x005C
(0047) else
(0048) {
(0049) AD9852_Clr_SDIO();
005A 9ABE SBI 0x17,6
005B 98C6 CBI 0x18,6
(0050) }
(0051) asm("nop");
005C 0000 NOP
(0052) AD9852_Set_SCLK();
005D 9ABB SBI 0x17,3
005E 9AC3 SBI 0x18,3
(0053) dat <<= 1;
005F 0F00 LSL R16
0060 9543 INC R20
0061 3048 CPI R20,0x8
0062 F378 BCS 0x0052
0063 940E0102 CALL pop_gset1
0065 9508 RET
FILE: D:\RJ\Project\AVR\AD9852\main.c
(0001) #include <iom16v.h>
(0002) #include "AD9852.h"
(0003)
(0004) //送入9852的数据缓冲区，初始化为控制寄存器值，使能PLL，5倍频，外部刷新
(0005) unsigned char AD9852_Data[]={0x10,0x45,0x00,0x60,0x00,0x00};
(0006)
(0007) void delay_us(unsigned int us)
(0008) {
(0009) while (--us);
_delay_us:
us --> R16
0066 01C8 MOVW R24,R16
0067 9701 SBIW R24,1
0068 018C MOVW R16,R24
0069 3000 CPI R16,0
006A 0701 CPC R16,R17
006B F7D1 BNE 0x0066
(0010) {
(0011) us++;
006C 5F0F SUBI R16,0xFF
006D 4F1F SBCI R17,0xFF
(0012) us--;
006E 5001 SUBI R16,1
006F 4010 SBCI R17,0
(0013) }
0070 9508 RET
_AD9852_DataPost:
i --> R20
DataLen --> R22
pDat --> R10
Addr --> R12
0071 940E00F9 CALL push_gset4
0073 0159 MOVW R10,R18
0074 2EC0 MOV R12,R16
0075 8568 LDD R22,Y+8
(0014) }
(0015)
(0016) void AD9852_DataPost(unsigned char Addr, unsigned char *pDat, unsigned char DataLen)
(0017) {
(0018) unsigned char i=0;
0076 2744 CLR R20
(0019)
(0020) AD9852_Set_IORESET();
0077 9ABD SBI 0x17,5
0078 9AC5 SBI 0x18,5
(0021) asm("nop");
0079 0000 NOP
(0022) AD9852_Clr_IORESET();
007A 9ABD SBI 0x17,5
007B 98C5 CBI 0x18,5
(0023)
(0024) i=Addr;
007C 2D4C MOV R20,R12
(0025) AD9852_ByteSend(i);
007D 2F04 MOV R16,R20
007E DFCF RCALL _AD9852_ByteSend
(0026)
(0027) for (i=0;i<DataLen;i++)
007F 2744 CLR R20
0080 C007 RJMP 0x0088
(0028) {
(0029) AD9852_ByteSend(pDat[i]);
0081 2FE4 MOV R30,R20
0082 27FF CLR R31
0083 0DEA ADD R30,R10
0084 1DFB ADC R31,R11
0085 8100 LDD R16,Z+0
0086 DFC7 RCALL _AD9852_ByteSend
0087 9543 INC R20
0088 1746 CP R20,R22
0089 F3B8 BCS 0x0081
(0030) }
(0031)
(0032) AD9852_Set_IOUD();
008A 9ABF SBI 0x17,7
008B 9AC7 SBI 0x18,7
(0033) asm("nop");
008C 0000 NOP
(0034) AD9852_Clr_IOUD();
008D 9ABF SBI 0x17,7
008E 98C7 CBI 0x18,7
008F 940E00F4 CALL pop_gset4
0091 9508 RET
_AD9852_Init:
0092 9721 SBIW R28,1
(0035) }
(0036)
(0037) void AD9852_Init()
(0038) {
(0039)
(0040) AD9852_CTRL_DDR |= ((0x01<<AD9852_IORESET)|(0x01<<AD9852_SCLK)|(0x01<<AD9852_MasterReset)|(0x01<<AD9852_CLKPOWER)|(0x01<<AD9852_IOUD)|(0x01<<AD9852_SDIO));
0093 B387 IN R24,0x17
0094 6E8D ORI R24,0xED
0095 BB87 OUT 0x17,R24
(0041)
(0042) AD9852_CTRL_PORT &= (~((0x01<<AD9852_CLKPOWER)|(0x01<<AD9852_IOUD)));
0096 B388 IN R24,0x18
0097 778B ANDI R24,0x7B
0098 BB88 OUT 0x18,R24
(0043) AD9852_CTRL_PORT |= ((0x01<<AD9852_IORESET)|(0x01<<AD9852_SCLK)|(0x01<<AD9852_MasterReset));
0099 B388 IN R24,0x18
009A 6289 ORI R24,0x29
009B BB88 OUT 0x18,R24
(0044)
(0045) delay_us(500);
009C EF04 LDI R16,0xF4
009D E011 LDI R17,1
009E DFC7 RCALL _delay_us
(0046)
(0047) AD9852_Clr_MasterReset(); //AD9852复位
009F 9AB8 SBI 0x17,0
00A0 98C0 CBI 0x18,0
(0048) asm("nop");
00A1 0000 NOP
(0049) AD9852_Set_MasterReset();
00A2 9AB8 SBI 0x17,0
00A3 9AC0 SBI 0x18,0
(0050) asm("nop");
00A4 0000 NOP
(0051) AD9852_Clr_MasterReset();
00A5 9AB8 SBI 0x17,0
00A6 98C0 CBI 0x18,0
(0052) asm("nop");
00A7 0000 NOP
(0053)
(0054) AD9852_DataPost(0x07,AD9852_Data,4); //送入初始控制字
00A8 E084 LDI R24,4
00A9 8388 STD Y+0,R24
00AA E620 LDI R18,0x60
00AB E030 LDI R19,0
00AC E007 LDI R16,7
00AD DFC3 RCALL _AD9852_DataPost
(0055) delay_us(1000);
00AE EE08 LDI R16,0xE8
00AF E013 LDI R17,3
00B0 DFB5 RCALL _delay_us
(0056) AD9852_Set_CLKPOWER(); //启动晶振
00B1 9ABA SBI 0x17,2
00B2 9AC2 SBI 0x18,2
00B3 9621 ADIW R28,1
00B4 9508 RET
_main:
00B5 9721 SBIW R28,1
(0057) }
(0058)
(0059) int main ()
(0060) {
(0061) DDRC = 0xff;
00B6 EF8F LDI R24,0xFF
00B7 BB84 OUT 0x14,R24
(0062) PORTC = 0xff;
00B8 BB85 OUT 0x15,R24
(0063)
(0064)
(0065) delay_us(2000);
00B9 ED00 LDI R16,0xD0
00BA E017 LDI R17,7
00BB DFAA RCALL _delay_us
(0066) delay_us(2000);
00BC ED00 LDI R16,0xD0
00BD E017 LDI R17,7
00BE DFA7 RCALL _delay_us
(0067)
(0068) AD9852_Init(); //AD9852初始化
00BF DFD2 RCALL _AD9852_Init
(0069) AD9852_DataPost(0x07,AD9852_Data,4); //送入初始控制字
00C0 E084 LDI R24,4
00C1 8388 STD Y+0,R24
00C2 E620 LDI R18,0x60
00C3 E030 LDI R19,0
00C4 E007 LDI R16,7
00C5 DFAB RCALL _AD9852_DataPost
(0070) delay_us(200);
00C6 EC08 LDI R16,0xC8
00C7 E010 LDI R17,0
00C8 DF9D RCALL _delay_us
(0071)
(0072) AD9852_Data[0]=0x0f; //满幅
00C9 E08F LDI R24,0xF
00CA 93800060 STS AD9852_Data,R24
(0073) AD9852_Data[1]=0xff;
00CC EF8F LDI R24,0xFF
00CD 93800061 STS AD9852_Data+1,R24
(0074) AD9852_DataPost(0x08,AD9852_Data,2);
00CF E082 LDI R24,2
00D0 8388 STD Y+0,R24
00D1 E620 LDI R18,0x60
00D2 E030 LDI R19,0
00D3 E008 LDI R16,0x8
00D4 DF9C RCALL _AD9852_DataPost
(0075) delay_us(200);
00D5 EC08 LDI R16,0xC8
00D6 E010 LDI R17,0
00D7 DF8E RCALL _delay_us
(0076)
(0077) AD9852_Data[0]=0x19; //10M
00D8 E189 LDI R24,0x19
00D9 93800060 STS AD9852_Data,R24
(0078) AD9852_Data[1]=0x99;
00DB E989 LDI R24,0x99
00DC 93800061 STS AD9852_Data+1,R24
(0079) AD9852_Data[2]=0x99;
00DE 93800062 STS AD9852_Data+2,R24
(0080) AD9852_Data[3]=0x99;
00E0 93800063 STS AD9852_Data+3,R24
(0081) AD9852_Data[4]=0x99;
00E2 93800064 STS 0x64,R24
(0082) AD9852_Data[5]=0x99;
00E4 93800065 STS 0x65,R24
(0083) AD9852_DataPost(0x02,AD9852_Data,6);
00E6 E086 LDI R24,6
00E7 8388 STD Y+0,R24
00E8 E620 LDI R18,0x60
00E9 E030 LDI R19,0
00EA E002 LDI R16,2
00EB DF85 RCALL _AD9852_DataPost
(0084) delay_us(200);
00EC EC08 LDI R16,0xC8
00ED E010 LDI R17,0
00EE DF77 RCALL _delay_us
(0085) while (1);
00EF CFFF RJMP 0x00EF
(0086) return 0;
FILE: <library>
00F0 2700 CLR R16
00F1 2711 CLR R17
00F2 9621 ADIW R28,1
00F3 9508 RET
pop_gset4:
00F4 E0E8 LDI R30,0x8
00F5 940C0103 JMP pop
push_gset5:
00F7 92FA ST R15,-Y
00F8 92EA ST R14,-Y
push_gset4:
00F9 92DA ST R13,-Y
00FA 92CA ST R12,-Y
push_gset3:
00FB 92BA ST R11,-Y
00FC 92AA ST R10,-Y
push_gset2:
00FD 937A ST R23,-Y
00FE 936A ST R22,-Y
push_gset1:
00FF 935A ST R21,-Y
0100 934A ST R20,-Y
0101 9508 RET
pop_gset1:
0102 E0E1 LDI R30,1
pop:
0103 9149 LD R20,Y+
0104 9159 LD R21,Y+
0105 FDE0 SBRC R30,0
0106 9508 RET
0107 9169 LD R22,Y+
0108 9179 LD R23,Y+
0109 FDE1 SBRC R30,1
010A 9508 RET
010B 90A9 LD R10,Y+
010C 90B9 LD R11,Y+
010D FDE2 SBRC R30,2
010E 9508 RET
010F 90C9 LD R12,Y+
0110 90D9 LD R13,Y+
0111 FDE3 SBRC R30,3
0112 9508 RET
0113 90E9 LD R14,Y+
0114 90F9 LD R15,Y+
0115 9508 RET
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