emif_sdram.c

TMS320VC5509A 用CSL配置EMIF的代码程序

#include <stdio.h>
#include <extaddr.h>
#include <csl.h>
#include <csl_pll.h>
#include <csl_emif.h>
#include <csl_chip.h>

#define  N  128

//#pragma DATA_SECTION(src,"section_xx")
//Uint16 src[N],i,j;    
//#pragma DATA_SECTION(dst,"section_yy")
//Uint16 dst[N],i,j;
//Uint32 address=0x20000;//SDRAM占据CE0和CE1两个片选空间，字地址从0X20000到0X400000共64Mbit
/*锁相环的设置*/
PLL_Config  myConfig      = {
  0,    //IAI: the PLL locks using the same process that was underway 
                //before the idle mode was entered
  1,    //IOB: If the PLL indicates a break in the phase lock, 
                //it switches to its bypass mode and restarts the PLL phase-locking 
                //sequence
  24,    //PLL multiply value; multiply 24 times
  1             //Divide by 2 PLL divide value; it can be either PLL divide value 
                //(when PLL is enabled), or Bypass-mode divide value
                //(PLL in bypass mode, if PLL multiply value is set to 1)
};
/*SDRAM的EMIF设置,采用的SDRAM存储器芯片为HY57V641620*/
EMIF_Config myemif = {
  0x0021, 	//EGCR  : the MEMFREQ = 00, SDRAM clkmem=cpu clock=144MHZ
  			//		  the WPE = 0 ,forbiden the writing posting when we debug the EMIF
  			//        the MEMCEN = 1,the memory clock is reflected on the CLKMEM pin
  			//        the NOHOLD = 1,HOLD requests are not recognized by the EMIF 
  0xFFFF,	//EMI_RST: any write to this register resets the EMIF state machine
  //CE0,CE1两个片选空间用作SDRAM,0x20000-0x400000
  0x3FFF,	//CE0_1:  CE0 space control register 1
  			//        MTYPE = 011,Synchronous DRAM(SDRAM),16-bit data bus width
  0xFFFF,   //CE0_2:  CE0 space control register 2
  0x00FF,   //CE0_3:  CE0 space control register 3
  			//        TIMEOUT = 0xFF;
  0x3FFF,	//CE1_1:  CE1 space control register 1
            //        MTYPE = 011,Synchronous DRAM(SDRAM),16-bit data bus width 
  0xFFFF,	//CE1_2:  CE1 space control register 2
  0x00FF,	//CE1_3:  CE1 space control register 3
  //CE2片选空间用作SRAM,0x400000-0x600000
  0x1316,	//CE2_1:  CE2 space control register 1 0x1316
            //        MTYPE = 001,SRAM,16-bit data bus width
            //READ SETUP=3(21ns),STROBE=5(35ns),HOLD=2(14ns)
  0x5115,	//CE2_2:  CE2 space control register 2 0x5115
            //READ EXT HOLD=WRITE EXT HOLD=1(14ns)
            //WRITE SETUP=1(7ns),STROBE=5(35ns),HOLD=1(7ns)
  0x00FF,	//CE2_3:  CE2 space control register 3
  //CE3片选空间用作外部数据输入，用来读VSP1221的转换数据
  0x1316,	//CE3_1:  CE3 space control register 1
            //         MTYPE = 001,SRAM,16-bit data bus width
            //READ SETUP=3(21ns),STROBE=5(35ns),HOLD=2(14ns)
  0xFFFF,	//CE3_2:  CE3 space control register 2
  0x00FF,	//CE3_3:  CE3 space control register 3
  //以下为SDRAM控制寄存器
  0x4922,   //SDC1:   SDRAM control register 1
  			//		  TRC = 9 
  			//        SDSIZE = 0;SDWID = 0   64Mbit
  			//        RFEN = 1
  			//        TRCD = 2
  			//        TRP  = 2
  0x0fff,	//SDPER : SDRAM period register
  			//		  7ns *4096
  0x07FF,   //SDINIT: SDRAM initialization register
  			//        any write to this register to init the all CE spaces,
  			//        do it after hardware reset or power up the C55x device
  0x0163	//SDC2:	  SDRAM control register 2
  			//        SDACC = 0;
  			//        TMRD = 01;
  			//        TRAS = 0110;
  			//        TACTV2ACTV = 0011;								
};


main()
{   
    Uint16 i,j;
	/*初始化CSL库*/	
    CSL_init();
    
    /*EMIF为全EMIF接口*/
    CHIP_RSET(XBSR,0x0a01);
    
    /*设置系统的运行速度为144MHz*/
    PLL_config(&myConfig);
    
    /*初始化DSP的外部SDRAM*/
    EMIF_config(&myemif);
    /*向SDRAM中写入数据*/
    //for(i=0;i<N;i++)
    //   {far_poke(address+i,i);}
    /*读出SDRAM中的数据*/
    for(i=0;i<128;i++)
        {
         far_poke(0x400000+i,22);
        }
    for(i=0;i<128;i++)
        {
         j=far_peek(0x400000+i);
         far_poke(0x30000+i,j) ;
        }
    while(1);
}
/******************************************************************************\
* End of pll2.c
\******************************************************************************/