📄 io86ch06.h
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#define TTREG2H _ttreg2_.byte[1]
extern Typ_IO __io(0x26) _tc1cr_; /* 0x14: Capture Register A */
#define TC1CR _tc1cr_.byte
extern Typ_IO __io(0x27) _tc3cr_; /* 0x14: Capture Register A */
#define TC3CR _tc3cr_.byte
#define TC3S _tc3cr_.bit.b3
extern Typ_IO __io(0x28) _tc4cr_; /* 0x14: Capture Register A */
#define TC4CR _tc4cr_.byte
#define TC4S _tc4cr_.bit.b3
extern Typ_IO __io(0x29) _tc5cr_; /* 0x14: Capture Register A */
#define TC5CR _tc5cr_.byte
#define TC5S _tc5cr_.bit.b3
extern Typ_IO __io(0x2a) _tc6cr_; /* 0x14: Capture Register A */
#define TC6CR _tc6cr_.byte
#define TC6S _tc6cr_.bit.b3
extern Typ_IO __io(0x2b) _sio2tdb_; /* 0x14: Capture Register A */
#define SIO2TDB _sio2cr_.byte
#define SIO2RDB SIO2TDB
/*=================*/
extern Typ_IOW __io(0x2c) _eirde_; /* 0x3a: interrupt enable register */
#define EIRDE _eirde_.word
#define EIRE _eirde_.byte[0]
#define EIRD _eirde_.byte[1]
#define EF23 _eirde_.W_IO.low.b7 // TC0 & INT5
#define EF22 _eirde_.W_IO.low.b6
#define EF21 _eirde_.W_IO.low.b5
#define EF20 _eirde_.W_IO.low.b4
#define EF19 _eirde_.W_IO.low.b3
#define EF18 _eirde_.W_IO.low.b2
#define EF17 _eirde_.W_IO.low.b1
#define EF16 _eirde_.W_IO.low.b0
extern Typ_IOW __io(0x2e) _ilde_; /* 0x3c: interrupt latch */
#define ILDE _ilde_.word
#define ILE _ilde_.byte[0]
#define ILD _ilde_.byte[1]
#define IL23 _ilde_.W_IO.low.b7
#define IL22 _ilde_.W_IO.low.b6
#define IL21 _ilde_.W_IO.low.b5
#define IL20 _ilde_.W_IO.low.b4
#define IL19 _ilde_.W_IO.low.b3
#define IL18 _ilde_.W_IO.low.b2
#define IL17 _ilde_.W_IO.low.b1
#define IL16 _ilde_.W_IO.low.b0
extern Typ_IO __io(0x31) _sio2cr_; /* 0x1e: UART0 control Register A */
#define SIO2CR _sio2cr_.byte
extern Typ_IO __io(0x32) _sio2sr2_; /* 0x1e: UART0 control Register A */
#define SIO2SR _sio2sr_.byte
extern Typ_IOW __io(0x34) _wdtcr_; /* 0x34: watchdog timer control register */
#define WDTCR _wdtcr_.word
#define WDTCR1 _wdtcr_.byte[0]
#define WDTCR2 _wdtcr_.byte[1]
#define WDTEN _wdtcr_.W_IO.low.b3
extern Typ_IO __io(0x36) _tbtcr_; /* 0x36: time base timer control register */
#define TBTCR _tbtcr_.byte
#define TBTEN _tbtcr_.bit.b3
#define DVOEN _tbtcr_.bit.b7
extern Typ_IO __io(0x37) _eintcr_; /* 0x37: external interrupt cntrol register */
#define EINTCR _eintcr_.byte
extern Typ_IO __io(0x38) _syscr1_; /* 0x38: system control register 1 */
#define SYSCR1 _syscr1_.byte
extern Typ_IO __io(0x39) _syscr2_; /* 0x39: system control register 2 */
#define SYSCR2 _syscr2_.byte
#define SYSCR21 _syscr2_
#define XEN _syscr2_.bit.b7
#define XTEN _syscr2_.bit.b6
#define SYSCK _syscr2_.bit.b5
#define IDLE _syscr2_.bit.b4
#define TGHALT _syscr2_.bit.b2
extern Typ_IOW __io(0x3a) _eirl_; /* 0x3a: interrupt enable register */
#define EIRW _eirl_.word
#define EIRL _eirl_.byte[0]
#define EIRH _eirl_.byte[1]
#define EF15 _eirl_.W_IO.high.b7 // TC0 & INT5
#define EF14 _eirl_.W_IO.high.b6
#define EF13 _eirl_.W_IO.high.b5
#define EF12 _eirl_.W_IO.high.b4
#define EF11 _eirl_.W_IO.high.b3
#define EF10 _eirl_.W_IO.high.b2
#define EF9 _eirl_.W_IO.high.b1
#define EF8 _eirl_.W_IO.high.b0
#define EF7 _eirl_.W_IO.low.b7
#define EF6 _eirl_.W_IO.low.b6
#define EF5 _eirl_.W_IO.low.b5 // INT1
#define EF4 _eirl_.W_IO.low.b4
#define IMF _eirl_.W_IO.low.b0
extern Typ_IOW __io(0x3c) _ill_; /* 0x3c: interrupt latch */
#define ILW _ill_.word
#define ILL _ill_.byte[0]
#define ILH _ill_.byte[1]
#define IL15 _ill_.W_IO.high.b7
#define IL14 _ill_.W_IO.high.b6
#define IL13 _ill_.W_IO.high.b5
#define IL12 _ill_.W_IO.high.b4
#define IL11 _ill_.W_IO.high.b3
#define IL10 _ill_.W_IO.high.b2
#define IL9 _ill_.W_IO.high.b1
#define IL8 _ill_.W_IO.high.b0
#define IL7 _ill_.W_IO.low.b7
#define IL6 _ill_.W_IO.low.b6
#define IL5 _ill_.W_IO.low.b5
#define IL4 _ill_.W_IO.low.b4
#define IL3 _ill_.W_IO.low.b3
#define IL2 _ill_.W_IO.low.b2
extern Typ_IO __io(0x3f) _psw_; /* 0x3f: Program Status Word */
#define PSW _psw_.byte
//#define CF _psw_.bit.b4
#endif
/*
* Copyright(C) 1990,91 TOSHIBA CORPORATION All rights reserved
*
********************************************************************
* Definition of Mask Patern for SFR
********************************************************************
*
* Mask patern for P0CR,P1CR,P6CR,P7CR
* P0CR(0x000a)
* P1CR(0x000b)
* P6CR(0x000c)
* P7CR(0x000d)
*/
#define WONLY7 0x80 /* Write only bit7 */
#define WONLY6 0x40 /* Write only bit6 */
#define WONLY5 0x20 /* Write only bit5 */
#define WONLY4 0x10 /* Write only bit4 */
#define WONLY3 0x08 /* Write only bit3 */
#define WONLY2 0x04 /* Write only bit2 */
#define WONLY1 0x02 /* Write only bit1 */
#define WONLY0 0x01 /* Write only bit0 */
/*
* TC1CR(0x0014)
*/
#define TFF1ON 0x80 /* TFF1=1 */
#define SCAP1ON 0x40 /* SCAP1=1 */
#define MCAP1ON 0x40 /* MCAP1=1 */
#define METT1ON 0x40 /* METT1=1 */
#define MPPG1ON 0x40 /* MPPG1=1 */
#define TC1S11 0x30 /* TC1S=11 */
#define TC1S10 0x20 /* TC1S=10 */
#define TC1S01 0x10 /* TC1S=01 */
#define TC1S00 0x00 /* TC1S=00 */
#define TC1CK11 0x0c /* TC1CK=11 */
#define TC1CK10 0x08 /* TC1CK=10 */
#define TC1CK01 0x04 /* TC1CK=01 */
#define TC1CK00 0x00 /* TC1CK=00 */
#define TC1M11 0x03 /* TC1M=11 */
#define TC1M10 0x02 /* TC1M=10 */
#define TC1M01 0x01 /* TC1M=01 */
#define TC1M00 0x00 /* TC1M=00 */
/*
* TC2CR(0x0015)
*/
#define TC2SON 0x20 /* TC2S=1 */
#define TC2CK111 0x1c /* TC1CK=11 */
#define TC2CK110 0x18 /* TC1CK=10 */
#define TC2CK101 0x14 /* TC1CK=01 */
#define TC2CK100 0x10 /* TC1CK=00 */
#define TC2CK011 0x0c /* TC1CK=11 */
#define TC2CK010 0x08 /* TC1CK=10 */
#define TC2CK001 0x04 /* TC1CK=01 */
#define TC2CK000 0x00 /* TC1CK=00 */
#define TC2MON 0x01 /* TC2=1 */
/*
* TC3CR(0x0016)
*/
#define SCAPON 0x80 /* SCAP=1 */
#define TC3SON 0x08 /* TC3S=0 */
#define TC3CK111 0x70 /* TC3CK=11 */
#define TC3CK110 0x60 /* TC3CK=10 */
#define TC3CK101 0x50 /* TC3CK=01 */
#define TC3CK100 0x40 /* TC3CK=00 */
#define TC3CK011 0x30 /* TC3CK=11 */
#define TC3CK010 0x20 /* TC3CK=10 */
#define TC3CK001 0x10 /* TC3CK=01 */
#define TC3CK000 0x00 /* TC3CK=00 */
#define TC3MON011 0x03 /* TC3M=1 */
#define TC3MON010 0x02 /* TC3M=1 */
#define TC3MON001 0x01 /* TC3M=1 */
#define TC3MON000 0x00 /* TC3M=1 */
/*
* TC4CR(0x0017)
*/
#define TFF4 0x80 /* TFF4=11 */
#define TC4SON 0x08 /* TC4S=1 */
#define TC4CK111 0x70 /* TC1CK=11 */
#define TC4CK110 0x60 /* TC1CK=10 */
#define TC4CK101 0x50 /* TC1CK=01 */
#define TC4CK100 0x40 /* TC1CK=00 */
#define TC4CK011 0x30 /* TC1CK=11 */
#define TC4CK010 0x20 /* TC1CK=10 */
#define TC4CK001 0x10 /* TC1CK=01 */
#define TC4CK000 0x00 /* TC1CK=00 */
#define TC4M111 0x07 /* TC1M=11 */
#define TC4M110 0x06 /* TC1M=10 */
#define TC4M101 0x05 /* TC1M=01 */
#define TC4M100 0x04 /* TC1M=00 */
#define TC4M011 0x03 /* TC1M=11 */
#define TC4M010 0x02 /* TC1M=10 */
#define TC4M001 0x01 /* TC1M=01 */
#define TC4M000 0x00 /* TC1M=00 */
/*
* SIOCR1(0x0026)
*/
#define SIOSON 0x80 /* SIOS=1 */
#define SIOINHON 0x40 /* SIOINH=1 */
#define SIOERM11 0x30 /* SIOM=011 */
#define SIOERM10 0x20 /* SIOM=001 */
#define SIOERM01 0x10 /* SIOM=011 */
#define SIOERM00 0x00 /* SIOM=001 */
#define SIODR 0x08 /* SIOM=001 */
#define SCK111 0x07 /* SCK=011 */
#define SCK110 0x06 /* SCK=010 */
#define SCK101 0x05 /* SCK=001 */
#define SCK100 0x04 /* SCK=000 */
#define SCK011 0x03 /* SCK=011 */
#define SCK010 0x02 /* SCK=010 */
#define SCK001 0x01 /* SCK=001 */
#define SCK000 0x00 /* SCK=000 */
/*
* SIOSR(0x0027)
*/
#define SIOF 0x80 /* ERM2=1 */
#define SEF 0x40 /* WAIT2=11 */
#define TXF 0x20 /* WAIT2=10 */
#define RXF 0x10 /* WAIT2=01 */
#define TXERR 0x08 /* WAIT2=00 */
#define RXERR 0x04 /* ERM1=1 */
/*
* WDTCR1(0x0034)
*/
#define WDTENON 0x08 /* WDTEN=1 */
#define WDTT11 0x06 /* WDTT=11 */
#define WDTT10 0x04 /* WDTT=10 */
#define WDTT01 0x02 /* WDTT=01 */
#define WDTT00 0x00 /* WDTT=00 */
#define WDTOUTON 0x01 /* WDTOUT=1 */
/*
* WDTCR2(0x0035)
*/
#define WDTCLR 0x4e /* WDT counter clear */
#define WDTDI 0xb1 /* WDT disable */
/*
* TBT(0x0036)
*/
#define DVOENON 0x80 /* DVO ON */
#define DVOCK3 0x60 /* DVOCK=11 */
#define DVOCK2 0x40 /* DVOCK=10 */
#define DVOCK1 0x20 /* DVOCK=01 */
#define DVOCK0 0x00 /* DVOCK=00 */
#define DV7CKON 0x10 /* DV7CK=1 */
#define TBTENON 0x08 /* TBT ON */
#define TBTCK7 0x07 /* TBTCK=111 */
#define TBTCK6 0x06 /* TBTCK=110 */
#define TBTCK5 0x05 /* TBTCK=101 */
#define TBTCK4 0x04 /* TBTCK=100 */
#define TBTCK3 0x03 /* TBTCK=011 */
#define TBTCK2 0x02 /* TBTCK=010 */
#define TBTCK1 0x01 /* TBTCK=001 */
#define TBTCK0 0x00 /* TBTCK=000 */
/*
* EINTCR(0x0037)
*/
#define INT1NCON 0x80 /* INT1NC=1 */
#define INT0ENON 0x40 /* INT0EN=1 */
#define INT0RNON 0xbf /* INT0EN=1 */
#define INT4RESON 0x20 /* INT4ES=1 */
#define INT4ESON 0x10 /* INT4ES=1 */
#define INT3ESON 0x08 /* INT3ES=1 */
#define INT2ESON 0x04 /* INT2ES=1 */
#define INT1ESON 0x02 /* INT1ES=1 */
#define INT4RSON 0x00 /* INT3ES=0 */
/*
* INTSEL(0x003E)
*/
#define INT5 0x01 /* INT1ES=1 */
#define INT4 0x02 /* INT3ES=0 */
/*
* SYSCR1(0x0038)
*/
#define STOPON 0x80 /* STOP=1 */
#define RELMON 0x40 /* RELM=1 */
#define RETMON 0x20 /* RETM=1 */
#define OUTENON 0x10 /* OUTEN=1 */
#define WUT11 0x0c /* DWUT=11 */
#define WUT10 0x08 /* DWUT=10 */
#define WUT01 0x04 /* DWUT=01 */
#define WUT00 0x00 /* DWUT=00 */
#define PONFON 0x01 /* PONF=1 */
/*
* SYSCR2(0x0039)
*/
#define XENON 0x80 /* XEN=1 */
#define XTENON 0x40 /* XTEN=1 */
#define SYSCKON 0x20 /* SYSCK=1 */
#define IDLEON 0x10 /* IDLE=1 */
#define TGHALT1 0x04 /* IDLE=1 */
/*
* EIR(0x003a/0x003b) Interrupt control
*/
/*
* GPSW(0x003f) Program status ward
*/
#define GRBS0 0x00 /* GRBS = 4 bit */
#define GRBS1 0x01 /* GRBS = 4 bit */
#define GRBS2 0x02 /* GRBS = 4 bit */
#define GRBS3 0x03 /* GRBS = 4 bit */
#define BHF 0x04 /* BHF = 1 bit */
#define BCF 0x05 /* BCF = 1 bit */
#define BZF 0x06 /* BZF = 1 bit */
#define BJF 0x07 /* BJF = 1 bit */
/*
* End of Definition of Standard Header for TMP86CH00N/F
*/
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