📄 io86ch06.h
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#include <stdlib.h>
#include "comdef.h"
#define _BaseSP 0x083f // Stack area initial address
#define _BaseIntTbl 0xffb0
#define RAM_TOP 0x0040 // Start address of RAM
#define RAM_SIZE _BaseSP-RAM_TOP+1 // Size of RAM
#if 1 // for TMP86CM47U
extern Typ_IO __io(0x00) _p0dr_; /* Port 0 */
#define P0DR _p0dr_.byte
#define IOP07 _p0dr_.bit.b7
#define IOP06 _p0dr_.bit.b6
#define IOP05 _p0dr_.bit.b5
#define IOP04 _p0dr_.bit.b4
#define IOP03 _p0dr_.bit.b3
#define IOP02 _p0dr_.bit.b2
#define IOP01 _p0dr_.bit.b1
#define IOP00 _p0dr_.bit.b0
/*
P0DR = 0xFC;
P0PRD = ;
*/
//#define LED_PORT P0DR
extern Typ_IO __io(0x01) _p1dr_; /* Port 1 */
#define P1DR _p1dr_.byte
#define IOP17 _p1dr_.bit.b7
#define IOP16 _p1dr_.bit.b6
#define IOP15 _p1dr_.bit.b5
#define IOP14 _p1dr_.bit.b4
#define IOP13 _p1dr_.bit.b3
#define IOP12 _p1dr_.bit.b2
#define IOP11 _p1dr_.bit.b1
#define IOP10 _p1dr_.bit.b0
/*
P1DR = 0xff;
P1CR = 0x01;
*/
/*--------------------------------------------------------------
[PORT 2] Variable Name : P2DR
Bit Name : P20 - P24
7 6 5 4 3 2 1 0
+-----+-----+-----+-----+-----+-----+-----+-----+
P2DR | | | | P24 | P23 | P22 | P21 | P20 |
(00002H) +-----+-----+-----+-----+-----+-----+-----+-----+
----------------------------------------------------------------*/
extern Typ_IO __io(0x02) _p2dr_; /* Port 2 */
#define P2DR _p2dr_.byte
#define IOP22 _p2dr_.bit.b2
#define IOP21 _p2dr_.bit.b1
#define IOP20 _p2dr_.bit.b0
/*
P2DR = 0xff;
P2CR = 0x01;
*/
extern Typ_IO __io(0x03) _p3dr_; /* Port 3 */
#define P3DR _p3dr_.byte
#define IOP37 _p3dr_.bit.b7
#define IOP36 _p3dr_.bit.b6
#define IOP35 _p3dr_.bit.b5
#define IOP34 _p3dr_.bit.b4
#define IOP33 _p3dr_.bit.b3
#define IOP32 _p3dr_.bit.b2
#define IOP31 _p3dr_.bit.b1
#define IOP30 _p3dr_.bit.b0
/*
P3DR = 0xef;
P3CR = 0x3d;
*/
extern Typ_IO __io(0x04) _p4dr_; /* Port 4 */
#define P4DR _p4dr_.byte
#define IOP47 _p4dr_.bit.b7
#define IOP46 _p4dr_.bit.b6
#define IOP45 _p4dr_.bit.b5
#define IOP44 _p4dr_.bit.b4
#define IOP43 _p4dr_.bit.b3
#define IOP42 _p4dr_.bit.b2
#define IOP41 _p4dr_.bit.b1
#define IOP40 _p4dr_.bit.b0
/*
P4DR = 0xff;
P4CR = 0x00;
*/
extern Typ_IO __io(0x05) _p5dr_; /* Port 4 */
#define P5DR _p5dr_.byte
#define IOP57 _p5dr_.bit.b7
#define IOP56 _p5dr_.bit.b6
#define IOP55 _p5dr_.bit.b5
#define IOP54 _p5dr_.bit.b4
#define IOP53 _p5dr_.bit.b3
#define IOP52 _p5dr_.bit.b2
#define IOP51 _p5dr_.bit.b1
#define IOP50 _p5dr_.bit.b0
/*
P5DR = 0xff;
P5CR = 0x00;
*/
extern Typ_IO __io(0x06) _p6dr_; /* Port 4 */
#define P6DR _p6dr_.byte
#define IOP67 _p6dr_.bit.b7
#define IOP66 _p6dr_.bit.b6
#define IOP65 _p6dr_.bit.b5
#define IOP64 _p6dr_.bit.b4
#define IOP63 _p6dr_.bit.b3
#define IOP62 _p6dr_.bit.b2
#define IOP61 _p6dr_.bit.b1
#define IOP60 _p6dr_.bit.b0
/*
P7DR = 0xff;
P7CR = 0x00;
*/
extern Typ_IO __io(0x07) _p7dr_; /* Port 4 */
#define P7DR _p7dr_.byte
#define IOP77 _p7dr_.bit.b7
#define IOP76 _p7dr_.bit.b6
#define IOP75 _p7dr_.bit.b5
#define IOP74 _p7dr_.bit.b4
#define IOP73 _p7dr_.bit.b3
#define IOP72 _p7dr_.bit.b2
#define IOP71 _p7dr_.bit.b1
#define IOP70 _p7dr_.bit.b0
/*
P7DR = 0xff;
P7CR = 0x00;
*/
/*=================*/
extern Typ_IO __io(0x0b) _p0prd_; /* 0x00: Port0 control register */
#define P0PRD _p0prd_.byte
#define IOP07IN _p0prd_.bit.b7
#define IOP06IN _p0prd_.bit.b6
#define IOP05IN _p0prd_.bit.b5
#define IOP04IN _p0prd_.bit.b4
#define IOP03IN _p0prd_.bit.b3
#define IOP02IN _p0prd_.bit.b2
#define IOP01IN _p0prd_.bit.b1
#define IOP00IN _p0prd_.bit.b0
extern Typ_IO __io(0x0c) _p2prd_; /* 0x00: Port0 control register */
#define P2PRD _p2prd_.byte
#define IOP22IN _p2prd_.bit.b2
#define IOP21IN _p2prd_.bit.b1
#define IOP20IN _p2prd_.bit.b0
extern Typ_IO __io(0x0d) _p3prd_; /* 0x00: Port0 control register */
#define P3PRD _p3prd_.byte
#define IOP37IN _p3prd_.bit.b7
#define IOP36IN _p3prd_.bit.b6
#define IOP35IN _p3prd_.bit.b5
#define IOP34IN _p3prd_.bit.b4
#define IOP33IN _p3prd_.bit.b3
#define IOP32IN _p3prd_.bit.b2
#define IOP31IN _p3prd_.bit.b1
#define IOP30IN _p3prd_.bit.b0
extern Typ_IO __io(0x0e) _p4prd_; /* 0x00: Port0 control register */
#define P4PRD _p4prd_.byte
#define IOP47IN _p4prd_.bit.b7
#define IOP46IN _p4prd_.bit.b6
#define IOP45IN _p4prd_.bit.b5
#define IOP44IN _p4prd_.bit.b4
#define IOP43IN _p4prd_.bit.b3
#define IOP42IN _p4prd_.bit.b2
#define IOP41IN _p4prd_.bit.b1
#define IOP40IN _p4prd_.bit.b0
extern Typ_IO __io(0x0f) _p5prd_; /* 0x00: Port0 control register */
#define P5PRD _p5prd_.byte
#define IOP57IN _p5prd_.bit.b7
#define IOP56IN _p5prd_.bit.b6
#define IOP55IN _p5prd_.bit.b5
#define IOP54IN _p5prd_.bit.b4
#define IOP53IN _p5prd_.bit.b3
#define IOP52IN _p5prd_.bit.b2
#define IOP51IN _p5prd_.bit.b1
#define IOP50IN _p5prd_.bit.b0
extern Typ_IO __io(0x08) _p0outcr_; /* 0x00: Port0 control register */
#define P0OUTCR _p0outcr_.byte
extern Typ_IO __io(0x09) _p1cr_; /* 0x02: Port3 control register */
#define P1CR _p1cr_.byte
extern Typ_IO __io(0x0a) _p4outcr_; /* 0x00: Port0 control register */
#define P4OUTCR _p4outcr_.byte
extern Typ_IO _p6cr1_; /* 0x02: Port3 control register */
#define P6CR1 _p6cr1_.byte
extern Typ_IO _p6cr2_; /* 0x02: Port3 control register */
#define P6CR2 _p6cr2_.byte
extern Typ_IO _p7cr1_; /* 0x02: Port3 control register */
#define P7CR1 _p7cr1_.byte
extern Typ_IO _p7cr2_; /* 0x02: Port3 control register */
#define P7CR2 _p7cr2_.byte
extern Typ_IO _uart1cr1_;
#define UART1CR1 _uart1cr1_.byte
#define UCLK000 0x00
#define UCLK001 0x01
#define UCLK010 0x02
#define UCLK011 0x03
#define UCLK100 0x04
#define UCLK101 0x05
#define UCLK110 0x06
#define UCLK111 0x07
#define UPE 0x08
#define EVEN 0x10
#define STBT 0x20
#define RE 0x40
#define TE 0x80
#define BRG 0x01 //at 8M 001 19200bit/s
#define URXE1 _uart1cr1_.bit.b6
#define UTXE1 _uart1cr1_.bit.b7
#define UART1SR _uart1cr1_.byte
#define TBEP _uart1cr1_.bit.b2
#define TEND _uart1cr1_.bit.b3
#define RBFL _uart1cr1_.bit.b4
#define OERR _uart1cr1_.bit.b5
#define FERR _uart1cr1_.bit.b6
#define PERR _uart1cr1_.bit.b7
extern Typ_IO _uart1cr2_;
#define UART1CR2 _uart1cr2_.byte
#define STOPBR 0x01
#define RXDNC00 0x00
#define RXDNC01 0x02
#define RXDNC10 0x04
#define RXDNC11 0x06
extern Typ_IO _tdbuf1_;
#define TDBUF1 _tdbuf1_.byte
#define RDBUF1 _tdbuf1_.byte
extern Typ_IO _uart2cr1_;
#define UART2CR1 _uart2cr1_.byte
#define URXE2 _uart2cr1_.bit.b6
#define UTXE2 _uart2cr1_.bit.b7
#define UART2SR _uart2cr1_.byte
#define TBEP2 _uart2cr1_.bit.b2
#define TEND2 _uart2cr1_.bit.b3
#define RBFL2 _uart2cr1_.bit.b4
#define OERR2 _uart2cr1_.bit.b5
#define FERR2 _uart2cr1_.bit.b6
#define PERR2 _uart2cr1_.bit.b7
extern Typ_IO _uart2cr2_;
#define UART2CR2 _uart2cr2_.byte
extern Typ_IO _tdbuf2_;
#define TDBUF2 _tdbuf2_.byte
#define RDBUF2 _tdbuf2_.byte
/*=================*/
extern Typ_IOW __io(0x10) _ttreg1a_; /* 0x10: Extend Timer0 Control Register */
#define TTREG1A _ttreg1a_.word
#define TREG1A _ttreg1a_.word
#define TTREG1AL _ttreg1a_.byte[0]
#define TTREG1AH _ttreg1a_.byte[1]
extern Typ_IOW __io(0x12) _ttreg1b_; /* 0x10: Extend Timer0 Control Register */
#define TREG1B _ttreg1b_.word
#define TTREG1B _ttreg1b_.word
#define TTREG1BL _ttreg1b_.byte
#define TTREG1BH _ttreg1b_.byte[1]
extern Typ_IO __io(0x14) _ttreg3_; /* 0x18: Compare Register */
#define TTREG3 _ttreg3_.byte
extern Typ_IO __io(0x15) _ttreg4_; /* 0x18: Compare Register */
#define TTREG4 _ttreg4_.byte
extern Typ_IO __io(0x16) _ttreg5_; /* 0x18: Compare Register */
#define TTREG5 _ttreg5_.byte
extern Typ_IO __io(0x17) _ttreg6_; /* 0x18: Compare Register */
#define TTREG6 _ttreg6_.byte
extern Typ_IO __io(0x18) _pwmreg3_; /* 0x18: Compare Register */
#define PWMREG3 _pwmreg3_.byte
extern Typ_IO __io(0x19) _pwmreg4_; /* 0x18: Compare Register */
#define PWMREG4 _pwmreg4_.byte
extern Typ_IO __io(0x1a) _pwmreg5_; /* 0x18: Compare Register */
#define PWMREG5 _pwmreg5_.byte
extern Typ_IO __io(0x1b) _pwmreg6_; /* 0x18: Compare Register */
#define PWMREG6 _pwmreg6_.byte
// adc
extern Typ_IO __io(0x1c) _adccr1_; /* 0x1a: UART0 control Register A */
#define ADCCR1 _adccr1_.byte
#define ADRS _adccr1_.bit.b7
#define ADCCR ADCCR1
extern Typ_IO __io(0x1d) _adccr2_; /* 0x1a: UART0 control Register A */
#define ADCCR2 _adccr2_.byte
extern Typ_IO __io(0x1e) _adcdr2_; /* 0x1a: UART0 control Register A */
#define ADCDR2 _adcdr2_.byte
#define EOCF _adcdr2_.bit.b5
extern Typ_IO __io(0x1f) _adcdr1_; /* 0x1a: UART0 control Register A */
#define ADCDR1 _adcdr1_.byte
#define ADCDR ADCDR1
//
extern Typ_IO __io(0x20) _siocr_; /* 0x26: Serial BUS Interface control Register 1 */
#define SIOCR1 _siocr_.byte
extern Typ_IO __io(0x21) _siosr_; /* 0x27: Serial BUS Interface control Register 2 */
#define SIOSR _siosr_.byte
extern Typ_U8 __io(0x22) _siodbr_; /* 0x28: SIO Tx/Rx Data Buffer Register */
#define SIORDB _siodbr_
#define SIOTDB _siodbr_
extern Typ_IO __io(0x23) _tc2cr_; /* 0x14: Capture Register A */
#define TC2CR _tc2cr_.byte
extern Typ_IOW __io(0x24) _ttreg2_; /* 0x10: Extend Timer0 Control Register */
#define TTREG2 _ttreg2_.word
#define TREG2 _ttreg2_.word
#define TTREG2L _ttreg2_.byte[0]
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