ctrl_rtl8019_regs.h

基于康草科技中一款SOPC开发板上的8019的以太网驱动程序

#include <io.h>

#ifndef _CTRL_RTL8019_REGS_H_
#define _CTRL_RTL8019_REGS_H_

/*
* There are four pages of registers, each paged in or out depending upon the
* value written to the command Register CR
*/

#define IOADDR_CTRL_RTL8019_CR(base)          __IO_CALC_ADDRESS_NATIVE(base, 0)      
#define IORD_CTRL_RTL8019_CR(base)            IORD(base, 0)
#define IOWR_CTRL_RTL8019_CR(base,data)       IOWR(base, 0, data)

#define CTRL_RTL8019_CR_STP_MSK                 0x1        
#define CTRL_RTL8019_CR_STP_OFST                0
#define CTRL_RTL8019_CR_STA_MSK                 0x2        
#define CTRL_RTL8019_CR_STA_OFST                1        
#define CTRL_RTL8019_CR_TXP_MSK                 0x4        
#define CTRL_RTL8019_CR_TXP_OFST                2 
#define CTRL_RTL8019_CR_RD0_MSK                 0x8        
#define CTRL_RTL8019_CR_RD0_OFST                3  
#define CTRL_RTL8019_CR_RD1_MSK                 0x10        
#define CTRL_RTL8019_CR_RD1_OFST                4  
#define CTRL_RTL8019_CR_RD2_MSK                 0x20        
#define CTRL_RTL8019_CR_RD2_OFST                5        
#define CTRL_RTL8019_CR_PS0_MSK                 0x40        
#define CTRL_RTL8019_CR_PS0_OFST                6    
#define CTRL_RTL8019_CR_PS1_MSK                 0x80        
#define CTRL_RTL8019_CR_PS1_OFST                7   

/* I/O data port */
#define IOADDR_CTRL_RTL8019_DATA(base)          __IO_CALC_ADDRESS_NATIVE(base, 0x10)      
#define IORD_CTRL_RTL8019_DATA(base)            IORD(base, 0x10)
#define IOWR_CTRL_RTL8019_DATA(base,data)       IOWR(base, 0x10, data)

/* Reset port */
#define IOADDR_CTRL_RTL8019_RESET(base)          __IO_CALC_ADDRESS_NATIVE(base, 0x1f)      
#define IORD_CTRL_RTL8019_RESET(base)            IORD(base, 0x1f)
#define IOWR_CTRL_RTL8019_RESET(base,data)       IOWR(base, 0x1f, data)
 
/*******************************
 * Page 0 register
 ******************************/

/* P0N1.R CLDA0 */
/* CLDA0, 1: Current Local DMA Registers (01H & 02H; Type=R in Page0)
 *           These two registers can be read to get the current local DMA address.
 */
#define IOADDR_CTRL_RTL8019_CLDA0(base)          __IO_CALC_ADDRESS_NATIVE(base, 1)      
#define IORD_CTRL_RTL8019_CLDA0(base)            IORD(base, 1)
/* P0N1.W PSTART 
 * Page Start Register (01H; Type=W in Page0, Type=R in Page 2)
 * The Page Start register sets the start page address of the receive buffer ring.
*/
#define IOADDR_CTRL_RTL8019_PSTART(base)          __IO_CALC_ADDRESS_NATIVE(base, 1)   
#define IOWR_CTRL_RTL8019_PSTART(base,data)       IOWR(base, 1, data)

/* P0N2.R CLDA1 */
#define IOADDR_CTRL_RTL8019_CLDA1(base)          __IO_CALC_ADDRESS_NATIVE(base, 2)      
#define IORD_CTRL_RTL8019_CLDA1(base)            IORD(base, 2)
/* PPN2.W PSTOP 
 * Page Stop Register (02H; Type=W in Page0, Type=R in Page2)
 * The Page Stop register sets the stop page address of the receive buffer ring. In 8 bit
 * mode the PSTOP register should not exceed to 0x60, in 16 bit mode the PSTOP
 * register should not exceed to 0x80.
 * */
#define IOADDR_CTRL_RTL8019_PSTOP(base)          __IO_CALC_ADDRESS_NATIVE(base, 2)   
#define IOWR_CTRL_RTL8019_PSTOP(base,data)       IOWR(base, 2, data)

/* P0N3RW BNRY 
 * Boundary Register (03H; Type=R/W in Page0)
 * This register is used to prevent overwrite of the receive buffer ring. It is typically
 * used as a pointer indicating the last receive buffer page the host has read.
*/
#define IOADDR_CTRL_RTL8019_BNRY(base)          __IO_CALC_ADDRESS_NATIVE(base, 3)      
#define IORD_CTRL_RTL8019_BNRY(base)            IORD(base, 3)
#define IOWR_CTRL_RTL8019_BNRY(base,data)       IOWR(base, 3, data)

/* P0N4.R TSR 
 * Transmit Status Register (04H; Type=R in Page0)
 * This register indicates the status of a packet transmission.
*/
#define IOADDR_CTRL_RTL8019_TSR(base)          __IO_CALC_ADDRESS_NATIVE(base, 4)      
#define IORD_CTRL_RTL8019_TSR(base)            IORD(base, 4)

/* This bit indicates the transmission completes with no errors. */
#define CTRL_RTL8019_TSR_PTX_MSK                 0x1        
#define CTRL_RTL8019_TSR_PTX_OFST                0
/* It indicates the transmission collided with some other station on the network. */
#define CTRL_RTL8019_TSR_COL_MSK                 0x4        
#define CTRL_RTL8019_TSR_COL_OFST                2
/* It indicates the NIC aborted the transmission because of excessive collisions. */
#define CTRL_RTL8019_TSR_ABT_MSK                 0x8        
#define CTRL_RTL8019_TSR_ABT_OFST                3
/* Carrier Sense lost bit is set when the carrier is lost during transmitting a packet. */
#define CTRL_RTL8019_TSR_CRS_MSK                 0x10        
#define CTRL_RTL8019_TSR_CRS_OFST                4
/* CD Heartbeat. The NIC watches for a collision signal (i.e. CD Heartbeat signal) during
 * the first 6.4us of the interframe gap following a transmission. This bit is set if the
 * transceiver fails to send this signal.
 */
#define CTRL_RTL8019_TSR_CDH_MSK                 0x40        
#define CTRL_RTL8019_TSR_CDH_OFST                6
/* Out of Window Collision. It is set when a collision is detected after a slot time (51.2us).
 * Transmissions are rescheduled as in normal collisions.
 */
#define CTRL_RTL8019_TSR_OWC_MSK                 0x80        
#define CTRL_RTL8019_TSR_OWC_OFST                7

/* P0N4.W TPSR 
 * Transmit Page Start Register (04H; Type=W in Page0)
 * This register sets the start page address of the packet to the transmitted.
*/
#define IOADDR_CTRL_RTL8019_TPSR(base)          __IO_CALC_ADDRESS_NATIVE(base, 4)   
#define IOWR_CTRL_RTL8019_TPSR(base,data)       IOWR(base, 4, data)

/* P0N5.R NCR 
 * Number of Collisions Register (05H; Type=R in Page0)
 * The register records the number of collisions a node experiences during a packet
 * transmission.
*/
#define IOADDR_CTRL_RTL8019_NCR(base)          __IO_CALC_ADDRESS_NATIVE(base, 5)      
#define IORD_CTRL_RTL8019_NCR(base)            IORD(base, 5)
/* P0N5.W TBCR0 
 * Transmit Byte Count Registers (05H & 06H; Type=W in Page0)
 * These two registers set the byte counts of the packet to be transmitted.
 */
#define IOADDR_CTRL_RTL8019_TBCR0(base)          __IO_CALC_ADDRESS_NATIVE(base, 5)   
#define IOWR_CTRL_RTL8019_TBCR0(base,data)       IOWR(base, 5, data)

/* P0N6.R FIFO 
 * First In First Out Register (06H; Type=R in Page0)
 * This register allows the host to examine the contents of the FIFO after loopback.
 */
#define IOADDR_CTRL_RTL8019_FIFO(base)          __IO_CALC_ADDRESS_NATIVE(base, 6)      
#define IORD_CTRL_RTL8019_FIFO(base)            IORD(base, 6)
/* 6.W TBCR1 
 * Transmit Byte Count Registers (05H & 06H; Type=W in Page0)
 * These two registers set the byte counts of the packet to be transmitted.
 */
#define IOADDR_CTRL_RTL8019_TBCR1(base)          __IO_CALC_ADDRESS_NATIVE(base, 6)   
#define IOWR_CTRL_RTL8019_TBCR1(base,data)       IOWR(base, 6, data)

/* P0N7RW ISR 
 * Interrupt Status Register (07H; Type=R/W in Page0)
 * This register reflects the NIC status. The host reads it to determine the cause of an interrupt.
 * Individual bits are cleared by writing a "1" into the corresponding bit. It must be cleared
 * after power up.
 */
#define IOADDR_CTRL_RTL8019_ISR(base)          __IO_CALC_ADDRESS_NATIVE(base, 7)      
#define IORD_CTRL_RTL8019_ISR(base)            IORD(base, 7)
#define IOWR_CTRL_RTL8019_ISR(base,data)       IOWR(base, 7, data)

/* This bit indicates packet received with no errors. */
#define CTRL_RTL8019_ISR_PRX_MSK                 0x01        
#define CTRL_RTL8019_ISR_PRX_OFST                0
/* This bit indicates packet transmitted with no errors. */
#define CTRL_RTL8019_ISR_PTX_MSK                 0x02        
#define CTRL_RTL8019_ISR_PTX_OFST                1
/* This bit is set when a packet received with one or more of the following errors:
 * - CRC error
 * - Frame alignment error
 * -Missed packe
*/
#define CTRL_RTL8019_ISR_RXE_MSK                 0x04        
#define CTRL_RTL8019_ISR_RXE_OFST                2
/* Transmit error bit is set when a packet transmission is aborted due to excessive
 * collisions.
*/
#define CTRL_RTL8019_ISR_TXE_MSK                 0x08        
#define CTRL_RTL8019_ISR_TXE_OFST                3
/* This bit is set when the receive buffer has been exhausted. */
#define CTRL_RTL8019_ISR_OVW_MSK                 0x10        
#define CTRL_RTL8019_ISR_OVW_OFST                4
/* Set when MSB of one or more of the network tally counters has been set. */
#define CTRL_RTL8019_ISR_CNT_MSK                 0x20        
#define CTRL_RTL8019_ISR_CNT_OFST                5
/* Set when remote DMA operation has been completed. */
#define CTRL_RTL8019_ISR_RDC_MSK                 0x40        
#define CTRL_RTL8019_ISR_RDC_OFST                6
/* This bit is set when NIC enters reset state and is cleared when a start command is
 * issued to the CR. It is also set when receive buffer overflows and is cleared when one or
 * more packets have been read from the buffer.
 */
#define CTRL_RTL8019_ISR_RST_MSK                 0x80        
#define CTRL_RTL8019_ISR_RST_OFST                7


/* P0N8.R CRDA0 
 * Current Remote DMA Address registers (08H & 09H; Type=R in Page0)
 * These two registers contain the current address of remote DMA.
 */
#define IOADDR_CTRL_RTL8019_CRDA0(base)          __IO_CALC_ADDRESS_NATIVE(base, 8)      
#define IORD_CTRL_RTL8019_CRDA0(base)            IORD(base, 8)
/* P0N8.W RSAR0 
 * Remote Start Address Registers (08H & 09H; Type=W in Page0)
 * These two registers set the start address of remote DMA.
 */
#define IOADDR_CTRL_RTL8019_RSAR0(base)          __IO_CALC_ADDRESS_NATIVE(base, 8)   
#define IOWR_CTRL_RTL8019_RSAR0(base,data)       IOWR(base, 8, data)

/* P0N9.R CRDA1 
 * Current Remote DMA Address registers (08H & 09H; Type=R in Page0)
 * These two registers contain the current address of remote DMA.
 */
#define IOADDR_CTRL_RTL8019_CRDA1(base)          __IO_CALC_ADDRESS_NATIVE(base, 9)      
#define IORD_CTRL_RTL8019_CRDA1(base)            IORD(base, 9)
/* P0N9.W RSAR1 
 * Remote Start Address Registers (08H & 09H; Type=W in Page0)
 * These two registers set the start address of remote DMA.
 */
#define IOADDR_CTRL_RTL8019_RSAR1(base)          __IO_CALC_ADDRESS_NATIVE(base, 9)   
#define IOWR_CTRL_RTL8019_RSAR1(base,data)       IOWR(base, 9, data)

/* P0NA.R 8019id0 */
#define IOADDR_CTRL_RTL8019_8019ID0(base)          __IO_CALC_ADDRESS_NATIVE(base, 0x0a)      
#define IORD_CTRL_RTL8019_8019ID0(base)            IORD(base, 0x0a)
/* P0NA.W RBCR0 
 * Remote Byte Count Registers (0AH & 0BH; Type=W in Page0)
 * These two registers se the data byte counts of remote DMA.
 */
#define IOADDR_CTRL_RTL8019_RBCR0(base)          __IO_CALC_ADDRESS_NATIVE(base, 0x0a)   
#define IOWR_CTRL_RTL8019_RBCR0(base,data)       IOWR(base, 0x0a, data)

/* P0NB.R 8019id1 */
#define IOADDR_CTRL_RTL8019_8019ID1(base)          __IO_CALC_ADDRESS_NATIVE(base, 0x0b)      
#define IORD_CTRL_RTL8019_8019ID1(base)            IORD(base, 0x0b)
/* P0NB.W RBCR1 
 * Remote Byte Count Registers (0AH & 0BH; Type=W in Page0)
 * These two registers se the data byte counts of remote DMA.
 */
#define IOADDR_CTRL_RTL8019_RBCR1(base)          __IO_CALC_ADDRESS_NATIVE(base, 0x0b)   
#define IOWR_CTRL_RTL8019_RBCR1(base,data)       IOWR(base, 0x0b, data)

/* P0NC.R RSR */
#define IOADDR_CTRL_RTL8019_RSR(base)          __IO_CALC_ADDRESS_NATIVE(base, 0x0c)      
#define IORD_CTRL_RTL8019_RSR(base)            IORD(base, 0x0C)

#define CTRL_RTL8019_RSR_PRX_MSK   0x01        
#define CTRL_RTL8019_RSR_PRX_OFST    0
#define CTRL_RTL8019_RSR_CRC_MSK   0x02        
#define CTRL_RTL8019_RSR_CRC_OFST    1
#define CTRL_RTL8019_RSR_FAE_MSK   0x04        
#define CTRL_RTL8019_RSR_FAE_OFST    2
#define CTRL_RTL8019_RSR_0_MSK   0x08        
#define CTRL_RTL8019_RSR_0_OFST    3
#define CTRL_RTL8019_RSR_MPA_MSK   0x10        
#define CTRL_RTL8019_RSR_MPA_OFST    4
#define CTRL_RTL8019_RSR_PHY_MSK   0x20        
#define CTRL_RTL8019_RSR_PHY_OFST    5
#define CTRL_RTL8019_RSR_DIS_MSK   0x40        
#define CTRL_RTL8019_RSR_DIS_OFST    6
#define CTRL_RTL8019_RSR_DFR_MSK   0x80        
#define CTRL_RTL8019_RSR_DFR_OFST    7

/* P0NC.W RCR */
#define IOADDR_CTRL_RTL8019_RCR(base)          __IO_CALC_ADDRESS_NATIVE(base, 0x0c)   
#define IOWR_CTRL_RTL8019_RCR(base,data)       IOWR(base, 0x0C, data)

#define CTRL_RTL8019_RCR_SEP_MSK                 0x01        
#define CTRL_RTL8019_RCR_SEP_OFST                0
#define CTRL_RTL8019_RCR_AR_MSK                 0x02        
#define CTRL_RTL8019_RCR_AR_OFST                1
#define CTRL_RTL8019_RCR_AB_MSK                 0x04        
#define CTRL_RTL8019_RCR_AB_OFST                2
#define CTRL_RTL8019_RCR_AM_MSK                 0x08        
#define CTRL_RTL8019_RCR_AM_OFST                3
#define CTRL_RTL8019_RCR_PRO_MSK                 0x10        
#define CTRL_RTL8019_RCR_PRO_OFST                4
#define CTRL_RTL8019_RCR_MON_MSK                 0x20        
#define CTRL_RTL8019_RCR_MON_OFST                5


/* P0ND.R CNTR0 */
#define IOADDR_CTRL_RTL8019_CNTR0(base)          __IO_CALC_ADDRESS_NATIVE(base, 0x0d)      
#define IORD_CTRL_RTL8019_CNTR0(base)            IORD(base, 0x0d)
/* P0ND.W TCR */
#define IOADDR_CTRL_RTL8019_TCR(base)          __IO_CALC_ADDRESS_NATIVE(base, 0x0D)   
#define IOWR_CTRL_RTL8019_TCR(base,data)       IOWR(base, 0x0D, data)

#define CTRL_RTL8019_TCR_CRC_MSK                 0x01        
#define CTRL_RTL8019_TCR_CRC_OFST                0
#define CTRL_RTL8019_TCR_LB0_MSK                 0x02        
#define CTRL_RTL8019_TCR_LB0_OFST                1
#define CTRL_RTL8019_TCR_LB1_MSK                 0x04        
#define CTRL_RTL8019_TCR_LB1_OFST                2
#define CTRL_RTL8019_TCR_ATD_MSK                 0x08        
#define CTRL_RTL8019_TCR_ATD_OFST                3
#define CTRL_RTL8019_TCR_OFST_MSK                 0x10        
#define CTRL_RTL8019_TCR_OFST_OFST                4