📄 can_settings.xml
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<PE_PROJECT_SETTINGS_DOCUMENTATION>
<PE_product_version v="version 3.01 for Freescale HC(S)08/RS08/CFV1"/>
<PE_core_version v="Processor Expert Version 0392"/>
<CPU_Bean name="Cpu" type="MC9S08DV16_48">
<Enabled v="Y"/>
<Properties>
<Bean_name v="Cpu"/>
<CPU_type v="MC9S08DV16CLF"/>
<list name="Shared Internal properties" v="1">
</list>
<list name="Shared CGM module settings" v="1">
<group name="Clock settings">
<group name="Internal clock">
<Internal_oscillator_frequency__kHz_ v="31.250000000000"/>
<Internal_ref__clock_for_peripherals v="Enabled"/>
<boolgroup name="Initialize trim value" v="yes">
<Trim_value_address v="65455"/>
<Fine_trim_value_address v="65454"/>
</boolgroup>
</group>
<boolgroup name="External clock" v="Enabled">
<enumgroup name="Clock source" v="External oscillator">
<Clock_frequency__MHz_ v="1"/>
<group name="Clock input pin">
<Pin_name v="PTG0_EXTAL"/>
<Pin_signal v=""/>
</group>
<Clock_range v="Low frequency"/>
<External_ref__clock_for_peripherals v="Enabled"/>
</enumgroup>
</boolgroup>
<group name="Low-power modes settings">
<boolgroup name="STOP instruction enabled" v="no" />
</group>
</group>
</list>
<Initialization_interrupt_priority v="interrupts enabled"/>
<list name="Shared internal resource mapping" v="1">
<group name="Internal resource mapping">
<group name="Interrupt vector table">
<Address v="65472"/>
<Size v="62"/>
</group>
<group name="Reset vector">
<Address v="65534"/>
<Size v="2"/>
</group>
</group>
</list>
<group name="Internal peripherals">
<list name="Shared Special Speed Mode Settings" v="1">
</list>
<list name="Shared ADC settings" v="1">
<group name="ADC">
<Internal_bandgap_buffer v="Disabled"/>
</group>
</list>
<list name="Shared BDM settings" v="1">
<group name="BDM pin support">
<BDM_pin v="BKGD_MS"/>
<BDM_pin_signal v=""/>
</group>
</list>
<list name="Shared Bus clock output settings" v="1">
<boolgroup name="Bus clock output" v="Disabled" />
</list>
<list name="Shared COP settings" v="1">
</list>
<list name="Shared FALSH settings" v="1">
<group name="FLASH">
<enumgroup name="Security state" v="Disabled">
</enumgroup>
<Protected_area v="Disabled"/>
<Vector_redirection v="no"/>
</group>
</list>
<list name="Included IO settings" v="1">
<group name="I/O module">
<group name="PORT A">
<Slew_rate_control_for_PTA0 v="no"/>
<Slew_rate_control_for_PTA1 v="no"/>
<Slew_rate_control_for_PTA2 v="no"/>
<Slew_rate_control_for_PTA3 v="no"/>
<Slew_rate_control_for_PTA4 v="no"/>
<Slew_rate_control_for_PTA5 v="no"/>
<Slew_rate_control_for_PTA6 v="no"/>
<Slew_rate_control_for_PTA7 v="no"/>
<Drive_strength_for_PTA0 v="High"/>
<Drive_strength_for_PTA1 v="High"/>
<Drive_strength_for_PTA2 v="High"/>
<Drive_strength_for_PTA3 v="High"/>
<Drive_strength_for_PTA4 v="High"/>
<Drive_strength_for_PTA5 v="High"/>
<Drive_strength_for_PTA6 v="High"/>
<Drive_strength_for_PTA7 v="High"/>
</group>
<group name="PORT B">
<Slew_rate_control_for_PTB0 v="no"/>
<Slew_rate_control_for_PTB1 v="no"/>
<Slew_rate_control_for_PTB2 v="no"/>
<Slew_rate_control_for_PTB3 v="no"/>
<Slew_rate_control_for_PTB4 v="no"/>
<Slew_rate_control_for_PTB5 v="no"/>
<Slew_rate_control_for_PTB6 v="no"/>
<Slew_rate_control_for_PTB7 v="no"/>
<Drive_strength_for_PTB0 v="High"/>
<Drive_strength_for_PTB1 v="High"/>
<Drive_strength_for_PTB2 v="High"/>
<Drive_strength_for_PTB3 v="High"/>
<Drive_strength_for_PTB4 v="High"/>
<Drive_strength_for_PTB5 v="High"/>
<Drive_strength_for_PTB6 v="High"/>
<Drive_strength_for_PTB7 v="High"/>
</group>
<group name="PORT D">
<Slew_rate_control_for_PTD0 v="no"/>
<Slew_rate_control_for_PTD1 v="no"/>
<Slew_rate_control_for_PTD2 v="no"/>
<Slew_rate_control_for_PTD3 v="no"/>
<Slew_rate_control_for_PTD4 v="no"/>
<Slew_rate_control_for_PTD5 v="no"/>
<Slew_rate_control_for_PTD6 v="no"/>
<Slew_rate_control_for_PTD7 v="no"/>
<Drive_strength_for_PTD0 v="High"/>
<Drive_strength_for_PTD1 v="High"/>
<Drive_strength_for_PTD2 v="High"/>
<Drive_strength_for_PTD3 v="High"/>
<Drive_strength_for_PTD4 v="High"/>
<Drive_strength_for_PTD5 v="High"/>
<Drive_strength_for_PTD6 v="High"/>
<Drive_strength_for_PTD7 v="High"/>
</group>
<group name="PORT E">
<Slew_rate_control_for_PTE0 v="no"/>
<Slew_rate_control_for_PTE2 v="no"/>
<Slew_rate_control_for_PTE3 v="no"/>
<Slew_rate_control_for_PTE4 v="no"/>
<Slew_rate_control_for_PTE5 v="no"/>
<Slew_rate_control_for_PTE6 v="no"/>
<Slew_rate_control_for_PTE7 v="no"/>
<Drive_strength_for_PTE0 v="High"/>
<Drive_strength_for_PTE2 v="High"/>
<Drive_strength_for_PTE3 v="High"/>
<Drive_strength_for_PTE4 v="High"/>
<Drive_strength_for_PTE5 v="High"/>
<Drive_strength_for_PTE6 v="High"/>
<Drive_strength_for_PTE7 v="High"/>
</group>
<group name="PORT F">
<Slew_rate_control_for_PTF0 v="no"/>
<Slew_rate_control_for_PTF1 v="no"/>
<Slew_rate_control_for_PTF2 v="no"/>
<Slew_rate_control_for_PTF3 v="no"/>
<Slew_rate_control_for_PTF4 v="no"/>
<Slew_rate_control_for_PTF5 v="no"/>
<Drive_strength_for_PTF0 v="High"/>
<Drive_strength_for_PTF1 v="High"/>
<Drive_strength_for_PTF2 v="High"/>
<Drive_strength_for_PTF3 v="High"/>
<Drive_strength_for_PTF4 v="High"/>
<Drive_strength_for_PTF5 v="High"/>
</group>
<group name="PORT G">
<Slew_rate_control_for_PTG0 v="no"/>
<Slew_rate_control_for_PTG1 v="no"/>
<Drive_strength_for_PTG0 v="High"/>
<Drive_strength_for_PTG1 v="High"/>
</group>
</group>
</list>
<list name="Shared LVD settings" v="1">
<boolgroup name="LVD module" v="Enabled">
<LVD_reset v="Enabled"/>
<boolgroup name="LVW interrupt" v="Disabled" />
<Enable_in_stop_mode v="yes"/>
<Low_voltage_detect_voltage v="Low trip point"/>
<Low_voltage_warning_voltage v="Low trip point"/>
</boolgroup>
</list>
<list name="Shared TMP1 settings" v="1">
</list>
<list name="Shared TMP1 settings" v="1">
</list>
</group>
<list name="Shared Cpu interrupts" v="1">
<group name="CPU interrupts">
<boolgroup name="Loss of lock" v="Disabled" />
<boolgroup name="SWI" v="Disabled" />
</group>
</list>
<list name="Shared MCG speed mode settings" v="1">
<group name="Enabled speed modes">
<boolgroup name="High speed mode" v="Enabled">
<High_speed_clock v="Internal Clock"/>
<Bus_freq__divider v="Auto select"/>
<Internal_bus_clock v="8"/>
<Fixed_freq__clock_clk_src_ v="Divided reference clock"/>
<Fixed_frequency_clock v="0.015625000000"/>
<Clock_monitor v="Disabled"/>
<enumgroup name="FLL/PLL mode" v="FLL Engaged">
<Loss_of_lock_interrupt v="Disabled"/>
<Ref_clock_source v="Internal Clock"/>
<Ref_clock_freq___MHz_ v="0.031250000000"/>
<Ref__clock_divider v="Auto select"/>
<Divided_ref_clock_freq___MHz_ v="0.031250000000"/>
<FLL_output_clock_freq___MHz_ v="32"/>
</enumgroup>
</boolgroup>
<boolgroup name="Low speed mode" v="Disabled" />
<boolgroup name="Slow speed mode" v="Disabled" />
</group>
</list>
</Properties>
<Methods>
<list name="SharedCpuMethods" v="1">
<SetHighSpeed v="don't generate code"/>
<SetLowSpeed v="don't generate code"/>
<SetSlowSpeed v="don't generate code"/>
<GetSpeedMode v="don't generate code"/>
<SetIntVect v="don't generate code"/>
<GetIntVect v="don't generate code"/>
<EnableInt v="generate code"/>
<DisableInt v="generate code"/>
<GetResetSource v="don't generate code"/>
<SetWaitMode v="don't generate code"/>
<SetStopMode v="don't generate code"/>
<GetLowVoltageWarningFlag v="don't generate code"/>
<ClearLowVoltageWarningFlag v="don't generate code"/>
<GetPartialPowerDownFlag v="don't generate code"/>
<ClearPartialPowerDownFlag v="don't generate code"/>
<GetIdentification v="don't generate code"/>
<SetBackdoorKey v="don't generate code"/>
<Delay100US v="don't generate code"/>
</list>
</Methods>
<Events>
<Event_module_name v="Events"/>
<list name="SharedCpuEvents" v="1">
<event name="OnReset" v="don't generate code" />
<event name="OnSwINT" v="don't generate code" />
<event name="OnLvwINT" v="don't generate code" />
<event name="OnLossOfLockINT" v="don't generate code" />
</list>
</Events>
<Compiler v="CodeWarrior HCS08 C Compiler"/>
<CompilerProperties>
<Compiler v="CodeWarrior HCS08 C Compiler"/>
<Generate_macros v="yes"/>
<group name="User initialization">
<User_data_declarations>
</User_data_declarations>
<User_code_before_PE_initialization>
</User_code_before_PE_initialization>
<User_code_after_PE_initialization>
</User_code_after_PE_initialization>
</group>
<Memory_model v="Small"/>
<boolgroup name="Generate PRM file" v="yes">
<enumgroup name="Stack specification" v="size">
<Stack_size v="128"/>
</enumgroup>
<Set_memory_areas_default v="Click to set default >"/>
<list name="ROM/RAM Areas" v="3">
<group name="Memory Area0">
<boolgroup name="ROM/RAM Area" v="Enabled">
<Name v="ROM"/>
<Address v="48640"/>
<Size v="16814"/>
<Qualifier v="READ_ONLY"/>
</boolgroup>
</group>
<group name="Memory Area1">
<boolgroup name="ROM/RAM Area" v="Enabled">
<Name v="Z_RAM"/>
<Address v="128"/>
<Size v="32"/>
<Qualifier v="READ_WRITE"/>
</boolgroup>
</group>
<group name="Memory Area2">
<boolgroup name="ROM/RAM Area" v="Enabled">
<Name v="RAM"/>
<Address v="160"/>
<Size v="992"/>
<Qualifier v="READ_WRITE"/>
</boolgroup>
</group>
</list>
</boolgroup>
</CompilerProperties>
</CPU_Bean>
</PE_PROJECT_SETTINGS_DOCUMENTATION>
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