📄 rom.lst
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C51 COMPILER V7.01 ROM 11/16/2007 15:52:11 PAGE 1
C51 COMPILER V7.01, COMPILATION OF MODULE ROM
OBJECT MODULE PLACED IN .\ROM.obj
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE ..\source\ROM.C BROWSE DEBUG OBJECTEXTEND LISTINCLUDE PRINT(.\ROM.lst) OBJE
-CT(.\ROM.obj)
stmt level source
1 #include "ROM_H.H"
1 =1 #include <reg52.h>
1 =2 /*--------------------------------------------------------------------------
2 =2 REG52.H
3 =2
4 =2 Header file for generic 80C52 and 80C32 microcontroller.
5 =2 Copyright (c) 1988-2001 Keil Elektronik GmbH and Keil Software, Inc.
6 =2 All rights reserved.
7 =2 --------------------------------------------------------------------------*/
8 =2
9 =2 /* BYTE Registers */
10 =2 sfr P0 = 0x80;
11 =2 sfr P1 = 0x90;
12 =2 sfr P2 = 0xA0;
13 =2 sfr P3 = 0xB0;
14 =2 sfr PSW = 0xD0;
15 =2 sfr ACC = 0xE0;
16 =2 sfr B = 0xF0;
17 =2 sfr SP = 0x81;
18 =2 sfr DPL = 0x82;
19 =2 sfr DPH = 0x83;
20 =2 sfr PCON = 0x87;
21 =2 sfr TCON = 0x88;
22 =2 sfr TMOD = 0x89;
23 =2 sfr TL0 = 0x8A;
24 =2 sfr TL1 = 0x8B;
25 =2 sfr TH0 = 0x8C;
26 =2 sfr TH1 = 0x8D;
27 =2 sfr IE = 0xA8;
28 =2 sfr IP = 0xB8;
29 =2 sfr SCON = 0x98;
30 =2 sfr SBUF = 0x99;
31 =2
32 =2 /* 8052 Extensions */
33 =2 sfr T2CON = 0xC8;
34 =2 sfr RCAP2L = 0xCA;
35 =2 sfr RCAP2H = 0xCB;
36 =2 sfr TL2 = 0xCC;
37 =2 sfr TH2 = 0xCD;
38 =2
39 =2
40 =2 /* BIT Registers */
41 =2 /* PSW */
42 =2 sbit CY = PSW^7;
43 =2 sbit AC = PSW^6;
44 =2 sbit F0 = PSW^5;
45 =2 sbit RS1 = PSW^4;
46 =2 sbit RS0 = PSW^3;
47 =2 sbit OV = PSW^2;
48 =2 sbit P = PSW^0; //8052 only
49 =2
50 =2 /* TCON */
51 =2 sbit TF1 = TCON^7;
52 =2 sbit TR1 = TCON^6;
C51 COMPILER V7.01 ROM 11/16/2007 15:52:11 PAGE 2
53 =2 sbit TF0 = TCON^5;
54 =2 sbit TR0 = TCON^4;
55 =2 sbit IE1 = TCON^3;
56 =2 sbit IT1 = TCON^2;
57 =2 sbit IE0 = TCON^1;
58 =2 sbit IT0 = TCON^0;
59 =2
60 =2 /* IE */
61 =2 sbit EA = IE^7;
62 =2 sbit ET2 = IE^5; //8052 only
63 =2 sbit ES = IE^4;
64 =2 sbit ET1 = IE^3;
65 =2 sbit EX1 = IE^2;
66 =2 sbit ET0 = IE^1;
67 =2 sbit EX0 = IE^0;
68 =2
69 =2 /* IP */
70 =2 sbit PT2 = IP^5;
71 =2 sbit PS = IP^4;
72 =2 sbit PT1 = IP^3;
73 =2 sbit PX1 = IP^2;
74 =2 sbit PT0 = IP^1;
75 =2 sbit PX0 = IP^0;
76 =2
77 =2 /* P3 */
78 =2 sbit RD = P3^7;
79 =2 sbit WR = P3^6;
80 =2 sbit T1 = P3^5;
81 =2 sbit T0 = P3^4;
82 =2 sbit INT1 = P3^3;
83 =2 sbit INT0 = P3^2;
84 =2 sbit TXD = P3^1;
85 =2 sbit RXD = P3^0;
86 =2
87 =2 /* SCON */
88 =2 sbit SM0 = SCON^7;
89 =2 sbit SM1 = SCON^6;
90 =2 sbit SM2 = SCON^5;
91 =2 sbit REN = SCON^4;
92 =2 sbit TB8 = SCON^3;
93 =2 sbit RB8 = SCON^2;
94 =2 sbit TI = SCON^1;
95 =2 sbit RI = SCON^0;
96 =2
97 =2 /* P1 */
98 =2 sbit T2EX = P1^1; // 8052 only
99 =2 sbit T2 = P1^0; // 8052 only
100 =2
101 =2 /* T2CON */
102 =2 sbit TF2 = T2CON^7;
103 =2 sbit EXF2 = T2CON^6;
104 =2 sbit RCLK = T2CON^5;
105 =2 sbit TCLK = T2CON^4;
106 =2 sbit EXEN2 = T2CON^3;
107 =2 sbit TR2 = T2CON^2;
108 =2 sbit C_T2 = T2CON^1;
109 =2 sbit CP_RL2 = T2CON^0;
2 =1 sfr P4 = 0xe8;
3 =1 sfr AUXR = 0X8E;
4 =1
5 =1 sbit P40=P4^0;
6 =1 sbit P41=P4^1;
C51 COMPILER V7.01 ROM 11/16/2007 15:52:11 PAGE 3
7 =1 sbit P42=P4^2;
8 =1
9 =1 #define uint unsigned int
10 =1 #define uchar unsigned char
11 =1
12 =1 #define ROM_RD_MODE1 0x00
13 =1 #define ROM_RD_MODE2 0x01
14 =1 #define ROM_RD_MODE3 0x50
15 =1 #define ROM_WR_MODE 0x80
16 =1
17 =1 #define PAGE_MODE 512
18 =1
19 =1 #define ROM_DATAPORT P0
20 =1
21 =1
22 =1 sbit ROM_BUSY = P1^4;
23 =1 sbit ROM_RD = P1^0;
24 =1 sbit ROM_CLE = P1^1;
25 =1 sbit ROM_ALE = P1^2;
26 =1 sbit ROM_WR = P1^3;
27 =1
28 =1 /*----------------------------------------------------------------
29 =1 ROM SUB PROGRAMS
30 =1 -----------------------------------------------------------------*/
31 =1 void rom_cs(bit flag);
32 =1 void rom_init(void);
33 =1
34 =1 unsigned char rom_erase_block(unsigned int add);
35 =1
36 =1 void rom_write_addcol(unsigned char value);
37 =1 void rom_write_addrow(unsigned int value);
38 =1
39 =1 void rom_write_com(unsigned char value);
40 =1 void rom_write_add(unsigned char value);
41 =1 void rom_write_data(unsigned char value);
42 =1
43 =1 void rom_rd_wr_data_start(uchar value,uchar addcol,uint addrow);
44 =1 void rom_write_block_data(uchar value);
45 =1 void rom_write_block_start(unsigned char addcol,unsigned int addrow);
46 =1 unsigned char rom_write_block_end();
47 =1 uchar rom_write_page(uint addcow,uchar xdata *p);
48 =1
49 =1 unsigned char rom_readID();
50 =1 void rom_read_block_start(unsigned char addcol,unsigned int addrow);
51 =1 uchar rom_read_block_byte(void);
52 =1 uint rom_read_block_word(void);
53 =1
54 =1
55 =1 /*----------------------------------------------------------------
56 =1 DELAY program
57 =1 -----------------------------------------------------------------*/
58 =1 extern void delay5us(uint utimes); //5uS*utimes IN 12MHZ
59 =1 extern void delay10ms(uint mtimes); //10MS*mtimes IN 12MHZ
60 =1
61 =1
2
3 void rom_init(void)
4 {
5 1 }
6
7 void rom_cs(bit flag)
8 { if(flag==0)
C51 COMPILER V7.01 ROM 11/16/2007 15:52:11 PAGE 4
9 1 { P40=1;
10 2 P41=0;
11 2 P42=0;
12 2 }
13 1 else
14 1 { P40=1;
15 2 P41=1;
16 2 P42=1;
17 2 }
18 1
19 1 }
20
21
22 uint READ_ROM_ID(void)
23 {
24 1 uint rrom_id;
25 1 ROM_RD=1;
26 1 rom_cs(0);
27 1 ROM_CLE=1;//COMMAND
28 1 ROM_ALE=0;
29 1 ROM_DATAPORT=0x90;
30 1 ROM_WR=0;
31 1 ROM_WR=1;
32 1 ROM_BUSY=1;
33 1 while(ROM_BUSY==0);
34 1
35 1 ROM_CLE=0;
36 1 ROM_ALE=1;
37 1 ROM_DATAPORT=00;
38 1 ROM_WR=0;
39 1 ROM_WR=1;
40 1 ROM_BUSY=1;
41 1 while(ROM_BUSY==0);
42 1
43 1 ROM_DATAPORT=0xff;
44 1 ROM_CLE=0; //read the data?!
45 1 ROM_ALE=0;//
46 1 ROM_RD=0;
47 1 rrom_id=ROM_DATAPORT;
48 1 ROM_RD=1;
49 1 ROM_BUSY=1;
50 1 while(ROM_BUSY==0);
51 1
52 1 ROM_RD=0;
53 1 rrom_id=(rrom_id<<8)|ROM_DATAPORT;
54 1 ROM_RD=1;
55 1 ROM_BUSY=1;
56 1 while(ROM_BUSY==0);
57 1
58 1 rom_cs(1);
59 1 return(rrom_id);
60 1 }
61
62
63 void rom_write_com(unsigned char value)
64 {
65 1 ROM_CLE=1;//COMMAND
66 1 ROM_ALE=0;
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