dm9000end.h

DM9000A的VXWORKS下驱动

#ifndef __INDm9000Endh
#define __INDm9000Endh

/* includes */

#ifdef __cplusplus
extern "C" {
#endif

IMPORT  int endMultiLstCnt (END_OBJ* pEnd);

#define UCHAR               unsigned char
#define UWORD               unsigned short int

#define DM9000_REG00        0x00
#define DM9000_REG05        0x30    /* SKIP_CRC/SKIP_LONG whz modify*/ 
#define DM9000_REG08        0x27   /*old =0x3f */
#define DM9000_REG09        0x38
#define DM9000_REG0A        0x08
#define DM9000_REGFF        0x83    /*0x8F 0x83    IMR */

#define DM9000_PHY          0x40    /* PHY address 0x01 */
#define DM9000_PKT_MAX      1536    /* Received packet max size */
#define DM9000_PKT_RDY      0x01    /* Packet ready to receive */
#define DM9000_MIN_IO       0x300
#define DM9000_MAX_IO       0x370
#define DM9000_INT_MII      0x00
#define DM9000_EXT_MII      0x80

#define DM9000_10MHD        0
#define DM9000_100MHD       1
#define DM9000_10MFD        4
#define DM9000_100MFD       5
#define DM9000_AUTO         8
#define DM9000_1M_HPNA      0x10

#define DM9000_MEDIA_MODE   DM9000_AUTO

#define FASTETHER_NIC       0
#define HOMERUN_NIC         1
#define LONGRUN_NIC         2

#define DM9801_NOISE_FLOOR  0x08
#define DM9802_NOISE_FLOOR  0x05

#define DM9000_DEV_NAME			"CPU_dm"	/*CPU----DM9000AE*/
#define DM9000_RE_DEV0_NAME     "Re0_dm"	/*RE----DM9000AE1*/
#define	DM9000_RE_DEV1_NAME		"Re1_dm"	/*RE----DM9000AE2*/
#define DM9000_DEV_NAME_LEN		7

/* Configuration items */

#define END_BUFSIZ      ETHERMTU/*(ETHERMTU + ENET_HDR_REAL_SIZ + 6)*/
#define EH_SIZE         (14)
#define END_SPEED_10M   10000000    /* 10Mbs */
#define END_SPEED_100M  100000000   /* 100Mbs */
#define END_SPEED       END_SPEED_100M


#undef htons
#define htons(x)  ((((x)&0xff00)>>8)|((x)&0x00ff)<<8)

/* Cache macros */

#define END_CACHE_INVALIDATE(address, len) \
        CACHE_DRV_INVALIDATE (&pDrvCtrl->cacheFuncs, (address), (len))

#define END_CACHE_PHYS_TO_VIRT(address) \
        CACHE_DRV_PHYS_TO_VIRT (&pDrvCtrl->cacheFuncs, (address))

#define END_CACHE_VIRT_TO_PHYS(address) \
        CACHE_DRV_VIRT_TO_PHYS (&pDrvCtrl->cacheFuncs, (address))

/*
 * Default macro definitions for BSP interface.
 * These macros can be redefined in a wrapper file, to generate
 * a new module with an optimized interface.
 */

/* Macro to connect interrupt handler to vector */
/* int vector is IRQ1 not (VOIDFUNCPTR *)0x118  */
/*#ifndef SYS_INT_CONNECT*/
#define SYS_INT_CONNECT(pDrvCtrl,rtn,arg,pResult) \
	{ \
    IMPORT STATUS sysIntConnect();  \
	*pResult = intConnect (IV_IRQ1, \
			     rtn, (int)arg); \
	}
/*#endif*/

/* Macro to disconnect interrupt handler from vector */

/*#ifndef SYS_INT_DISCONNECT*/
#define SYS_INT_DISCONNECT(pDrvCtrl,rtn,pResult) \
	{ \
   *pResult = OK; /* HELP: need a real routine */ \
   }
/*#endif*/

/* A shortcut for getting the hardware address from the MIB II stuff. */

#define END_HADDR(pEnd) \
        ((pEnd)->mib2Tbl.ifPhysAddress.phyAddress)

#define END_HADDR_LEN(pEnd) \
        ((pEnd)->mib2Tbl.ifPhysAddress.addrLength)
    
IMPORT STATUS   cacheArchInvalidate (CACHE_TYPE, void *, size_t);
IMPORT STATUS   cacheArchFlush (CACHE_TYPE, void *, size_t);


/* The definition of the driver control structure */
typedef struct end_device
{
    END_OBJ             end;            /* The class we inherit from. */
    END_ERR             err;
    int                 unit;           /* unit number */
    int                 ivec;           /* interrupt vector */
    int                 ilevel;         /* interrupt level */
    long                flags;          /* Our local flags. */
    UCHAR               enetAddr[6];    /* ethernet address */

    CACHE_FUNCS         cacheFuncs;     /* cache function pointers */
    CL_POOL_ID          pClPoolId;      /* cluster pool */
    BOOL                rxHandling;     /* rcv task is scheduled */

    UCHAR               io_mode;        /* 0:word, 2:byte */
    char                tx_pkt_cnt;
    char                device_wait_reset;
    UWORD               queue_pkt_len;
    UCHAR               reg0;           /* registers saved */
    UCHAR               nic_type;       /* NIC type */
    UCHAR               op_mode;        /* PHY operation mode */

    UCHAR               mcastFilter[8]; /* multicast filter */
    int                 txBuf[ETHERMTU + EH_SIZE + 6 + 64];
} END_DEVICE;


/* typedefs */

typedef struct
{
    int len;
    char * pData;
} PKT;  /* A dummy DMA data packet */

#define DM9000_PKT_LEN_GET(pPkt) (((PKT *)pPkt)->len)
#define DM9000_PKT_DATA_GET(pPkt) (((PKT *)pPkt)->pData)

typedef struct rfd
{
    PKT *  pPkt;
    struct rfd * next;
} RFD;  /* dummy rx frame descriptor */


NET_POOL dm9000CmpNetPool;

/* Definitions for the flags field */

#define DM9000_PROMISCUOUS  0x1
#define DM9000_POLLING      0x2

/* Status register bits, returned by dm9000StatusRead() */

#define DM9000_RINT         0x1     /* Rx interrupt pending */
#define DM9000_TINT         0x2     /* Tx interrupt pending */
#define DM9000_VALID_INT    0x3     /* Any valid interrupt pending */
#define DM9000_RXON         0x4     /* Rx on (enabled) */
#define DM9000_TFULL        0x8     /* tx full */
#define DM9000_RXRDY        0x10    /* data rdy */

#define DM9000_MIN_FBUF     (1536)  /* min first buffer size */


#define DM9000A_Data_PORT	(volatile UINT16 *)(0x80000080+0x304)
#define DM9000A_Addr_PORT	(volatile UINT16 *)(0x80000000+0x300)
#define DM9000A1_Data_PORT	(volatile UINT16 *)(0x70000080+0x304)
#define DM9000A1_Addr_PORT	(volatile UINT16 *)(0x70000000+0x300) 
#define DM9000A2_Data_PORT	(volatile UINT16 *)(0x70000080+0x304)
#define DM9000A2_Addr_PORT	(volatile UINT16 *)(0x70000000+0x300) 






#define  INT_LOCK()	
#define  INT_UNLOCK(x)	



#endif /* __INCmotFecEndh */