usb_otg_dev_lib.c

三星 S3C2460 USB OTG监控代码

/*******************************************************************************
* File Name    : usb_otg_dev_lib.c
* Description  : S3C2460A USB OTG library functions
* Author       : Haksoo Kim
* Dept         : Mobile solution, AP
* Created Date : 2005.06.02
* Version      : 1.0
* History
*   R1.0 (2005.06.02): First Release
********************************************************************************/  

#include <string.h>

#include "Option.h"
#include "2460addr.h"
#include "2460lib.h"

#include "2460usb_otg_dev.h"
#include "usb_otg.h"
#include "usb_otg_dev_main.h"
#include "usb_otg_dev_lib.h"
#include "usb_otg_dev_setup.h"
#include "usb_otg_dev_main.h"

void ConfigUsbOtgDev(void)
{

    ReconfigUsbOtgDev();

    rINTMSK&=~(BIT_USB);  
    rINTSUBMSK&=~(BIT_SUB_OTG); 
    
}

void ReconfigUsbOtgDev(void)
{
	uint32 i;
// *** End point information ***
//   EP0: control
//   EP1: bulk in end point
//   EP2: not used
//   EP3: bulk out end point
//   EP4: not used
	
	//* MAC REGISTER
	apOTG_MAC_DEV->EP[OTG_DEV_CTRL_ENDP].info = OTG_DEV_EP0_PKT_SIZE | 0<<15 | 0<<11 | 0<<7 | OTG_DEV_EP_CONTROL | OTG_DEV_EP_DIR_OUT | OTG_DEV_CTRL_ENDP<<0;
	apOTG_MAC_DEV->EP[OTG_DEV_BULKIN_ENDP].info = OTG_DEV_EP1_PKT_SIZE | 0<<15 | 0<<11 | 1<<7 | OTG_DEV_EP_BULK | OTG_DEV_EP_DIR_IN | OTG_DEV_BULKIN_ENDP<<0;
	apOTG_MAC_DEV->EP[OTG_DEV_BULKOUT_ENDP].info = OTG_DEV_EP3_PKT_SIZE | 0<<15 | 0<<11 | 1<<7 | OTG_DEV_EP_BULK | OTG_DEV_EP_DIR_OUT | OTG_DEV_BULKOUT_ENDP<<0;

	//* Disable and clear interrupts
	apOTG_TLI_DEV_G->devIntrMask = 0;
	apOTG_TLI_DEV_G->epIntrMask = 0;
	apOTG_TLI_DEV_G->devIntr = ~0x0;
	apOTG_TLI_DEV_G->epIntr = ~0x0;
	
	//* Init FIFO size registers
	apOTG_TLI_DEV_G->rxfifoSize = OTG_RX_FIFO_SIZE>>2;	//unit : DWORDs
	apOTG_TLI_DEV_S->InEP[OTG_DEV_CTRL_ENDP].txfifoSize = OTG_TX_FIFO_SIZE>>2;	//unit : DWORDs
	apOTG_TLI_DEV_S->InEP[OTG_DEV_BULKIN_ENDP].txfifoSize = OTG_TX_FIFO_SIZE>>2;	//unit : DWORDs

	//* Reset the device
	UsbOtg_ResetDev();
	
	//* Init threshold register
	apOTG_TLI_DEV_G->threshold = (OTG_RX_FIFO_SIZE>>2)<<16 | 0<<0;	//no rx/tx threshold interrupt
	
	//* Set RX FIFO ready so we can receive packets */
	apOTG_TLI_DEV_S->OutEP[OTG_DEV_CTRL_ENDP].control = OTG_DEV_RX_FIFOREADY;
	apOTG_TLI_DEV_S->OutEP[OTG_DEV_BULKOUT_ENDP].control = OTG_DEV_RX_FIFOREADY;
	
	//* Enable interrupts */
	//apOTG_TLI_DEV_G->devIntrMask = OTG_DEV_RX_FIFO_INTR | OTG_DEV_SETUP_INTR | OTG_DEV_BUSRESET_INTR | OTG_DEV_SETCFG_INTR;
	apOTG_TLI_DEV_G->devIntrMask = OTG_DEV_RX_FIFO_INTR | OTG_DEV_SETUP_INTR | OTG_DEV_SETCFG_INTR;
	apOTG_TLI_DEV_G->epIntrMask = 0x03;	//enable inEP0, inEP1 interrupt	
	
	//* Set configuration
	/* NOTE!!! some delay is necessary */
	for(i=0;i<0x1000;)i++;
	apOTG_TLI_DEV_G->devConfig = OTG_DEV_DEVICE_MODE;
	for(i=0;i<0x1000;)i++;
	apOTG_TLI_DEV_G->devConfig |= OTG_DEV_CONFIG_SELFPOWERED;
	for(i=0;i<0x1000;)i++;
	apOTG_TLI_DEV_G->devConfig |= OTG_DEV_CONFIG_SPEEDFULL;	
	
	ep0State=EP0_STATE_INIT;

	return;
    
}

void UsbOtg_ResetDev(void)
{
	//* Clear interrupts
	apOTG_TLI_DEV_G->setupStatus = OTG_DEV_SETUP_STATUS_INTR;
	apOTG_TLI_DEV_G->rxStatus = OTG_DEV_RX_STATUS_INTR;
	apOTG_TLI_DEV_G->devIntr = OTG_DEV_RX_FIFO_INTR | OTG_DEV_SETUP_INTR | OTG_DEV_BUSRESET_INTR;

	//* Flush fifo & clear EP status bits
	apOTG_TLI_DEV_S->OutEP[OTG_DEV_CTRL_ENDP].control = OTG_DEV_RX_FLUSHFIFO;
	apOTG_TLI_DEV_S->InEP[OTG_DEV_CTRL_ENDP].status = OTG_DEV_TX_NAK_INTR | OTG_DEV_TX_STATUS_INTR;
	apOTG_TLI_DEV_S->InEP[OTG_DEV_CTRL_ENDP].control = OTG_DEV_TX_FLUSHFIFO;
	apOTG_TLI_DEV_S->OutEP[OTG_DEV_BULKOUT_ENDP].control = OTG_DEV_RX_FLUSHFIFO;
	apOTG_TLI_DEV_S->InEP[OTG_DEV_BULKIN_ENDP].status = OTG_DEV_TX_NAK_INTR | OTG_DEV_TX_STATUS_INTR;
	apOTG_TLI_DEV_S->InEP[OTG_DEV_BULKIN_ENDP].control = OTG_DEV_TX_FLUSHFIFO;
	
	ep0State=EP0_STATE_INIT;
}


void RdPktEp0(unsigned char *buf,int num)
{
	int i;

	for(i=0;i<num;i++)
	{
		buf[i]=(unsigned char)rEP0_FIFO;	
	}
}
    
//->
//khs.050117
//	modified for debug
#ifdef KHS_USBD_DEBUG	//new>>
extern Usbd_Ep0_Data_s Usbd_Ep0_Data[100];
extern unsigned char count_Ep0_Data;
extern unsigned int ep0State;
void WrPktEp0(unsigned char *buf,int num)
{
    int i;  
       
    for(i=0;i<num;i++)
    {    		
        *ptrTxFifo0++=buf[i];	
    }
    
    Usbd_Ep0_Data[count_Ep0_Data].state=ep0State;
	Usbd_Ep0_Data[count_Ep0_Data].direction=1;	//host->device
	for(i=0;i<num;i++)
		Usbd_Ep0_Data[count_Ep0_Data].data[i]=buf[i];
	Usbd_Ep0_Data[count_Ep0_Data].cnt=num;
	count_Ep0_Data++;
    
}
#else	//org>>
void WrPktEp0(unsigned char *buf,int num)
{
    int i;
    
       
    for(i=0;i<num;i++)
    {    		
        *ptrTxFifo0++=buf[i];	
    }	

}
#endif
//<-

void WrByteEp0(unsigned char value)
{
	*ptrTxFifo0++= value;
}


void WrPktEp1(unsigned char *buf,int num)
{
    int i;
    	
    for(i=0;i<num;i++)
    {
        *ptrTxFifo1++=buf[i];	
    }
}

void RdPktEp3(uint8 *buf,int num)
{
    int i,j;
    char a,b;
    uint32 temp;
    
    a=num/4;
    b=num%4;
    	
    for(i=0;i<a;i++)
    {
        *((uint32*)buf)++ = (uint32)*ptrRxFifo++;
    }
    if(b!=0)
    {
    	temp = (uint32)*ptrRxFifo++;
        for(j=0;j<b;j++)
        {
        	*((uint8 *)buf)++ = temp & 0xff;
        	temp >>= 8;
	    }
    }
}

#if USBOTG_DMA
uint8 dma_first = 1;
void ConfigEp3DmaMode(unsigned int bufAddr,unsigned int count)
{
    int i,word_count,burst_count;    
    
    rINTMSK|=(BIT_USB);  
    rINTSUBMSK|=(BIT_SUB_OTG); 
    
    rINTMSK&=~(BIT_DMA_SBUS);
    rINTSUBMSK&=~(BIT_SUB_DMA2);
        	    
	rDISRC2=(uint32)OTG_DEV_RX_FIFO;
	
    if(dma_first == 1)
	{
	    rDISRCC2=(0<<1)|(0<<0); //src=AHB,increment
	    
	    rDIDSTC2=(0<<1)|(0<<0);

	#if USBOTG_UNIT_DMA
	   	word_count = (count/4);
	   	
	    //rDCON2=(word_count)|(1u<<31)|(1<<30)|(1<<29)|(0<<28)|(1<<27)|(1<<23)|(0<<22)|(2<<20); 
	        //handshake,requestor=AHB,CURR_TC int enable,unit transfer,
	        //whole service,src=USBD,H/W request,autoreload,word,CURR_TC
	    
	    rDCON2=(word_count)|(1u<<31)|(1<<30)|(1<<29)|(0<<28)|(0<<27)|(1<<23)|(0<<22)|(2<<20); 
	        //handshake,requestor=AHB,CURR_TC int enable,unit transfer,
	        //single service,src=USBD,H/W request,autoreload,word,CURR_TC
	#else //burst
		burst_count = count/16;
		
	    //rDCON2=(burst_count)|(1u<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<23)|(0<<22)|(2<<20); 
	        //handshake,requestor=AHB,CURR_TC int enable,unit transfer,
	        //whole service,src=USBD,H/W request,autoreload,word,CURR_TC
	    
	    rDCON2=(burst_count)|(1u<<31)|(1<<30)|(1<<29)|(1<<28)|(0<<27)|(1<<23)|(0<<22)|(2<<20); 
	        //handshake,requestor=AHB,CURR_TC int enable,unit transfer,
	        //single service,src=USBD,H/W request,autoreload,word,CURR_TC
	#endif
	        
	    rDMAREQSEL2=(27<<1)|(1<<0);
		
		dma_first = 0;
	}   	    
	
    rDIDST2=bufAddr;       //dst=AHB,increase,dst=bufAddr
    rDMASKTRIG2= (1<<1); 
   
   #if USBOTG_UNIT_DMA
    rOTG_DEV_DIU_OUT_EP3_DMA = (count<<16) | (2<<12) | (2<<6) | (2<<2);
   #else //burst
    rOTG_DEV_DIU_OUT_EP3_DMA = (count<<16) | (2<<12) | (2<<6) | (4<<2);
   #endif   
    
    rOTG_DEV_DIU_OUT_EP3_DMA |= 0x1;	//DMA active
    
    //wait until DMA_CON is effective.
    while((rDSTAT2&0xfffff)==0);
}
#endif

void ConfigEp3IntMode(void)
{
    
    rDMASKTRIG2 = (0<<1);  // EP3=DMA ch 2
    
    //rOTG_DEV_DIU_OUT_EP3_DMA = 0x0;	//DMA de-activate
	
    //dma disable
    while(rOTG_DEV_DIU_OUT_EP3_DMA!=0)
    {
    	rOTG_DEV_DIU_OUT_EP3_DMA=0;
    }

	apOTG_TLI_DEV_S->OutEP[OTG_DEV_BULKOUT_ENDP].control |= OTG_DEV_RX_FLUSHFIFO;
	
	//* Initialize pointer to Rx FIFO
	ptrRxFifo = OTG_DEV_RX_FIFO;
	
	apOTG_TLI_DEV_S->OutEP[OTG_DEV_BULKOUT_ENDP].control |= OTG_DEV_RX_FIFOREADY;

    rINTMSK|=(BIT_DMA_SBUS);
    rINTSUBMSK|=(BIT_SUB_DMA2);
    
    rINTMSK&=~(BIT_USB);  
    rINTSUBMSK&=~(BIT_SUB_OTG); 
    
    return;
    
}