option.h

三星S3C2460 USB DEVICE /USB HOST 监控代码

#ifndef __OPTION_H__
#define __OPTION_H__

#ifdef __cplusplus
extern "C" {
#endif

#include "Def.h"

#define		SEMIHOSTING	FALSE

#if	(WHICH_PORT == 1)	//400 or 496PKG
#define 	_NONCACHE_STARTADDRESS		0x11000000
#define 	_RAM_STARTADDRESS			0x10000000
#define 	_MMUTT_STARTADDRESS			0x10028000
#define 	_ISR_STARTADDRESS			0x1002ff00
#define		_MEMORY_ENDADDRESS			0x12000000
#else	//416PKG
#define 	_NONCACHE_STARTADDRESS		0x21000000
#define 	_RAM_STARTADDRESS			0x20000000
#define 	_MMUTT_STARTADDRESS			0x20028000
#define 	_ISR_STARTADDRESS			0x2002ff00
#define		_MEMORY_ENDADDRESS			0x22000000
#endif


//=====================================================================================
//	(62,3,1)=84Mhz,  (42,1,1)=100Mhz, (54,1,1)=124Mhz, (68,4,0)=152Mhz, (62,3,0)=168Mhz
//	(42,1,0)=200Mhz, (60,2,0)=204Mhz, (47,1,0)=220Mhz, (72,2,0)=240Mhz, (79,2,0)=261Mhz
//	(86,2,0)=282Mhz, (92,2,0)=300Mhz

#define		FIN					12000000

#define		Startup_MDIV		42
#define		Startup_PDIV		1
#define		Startup_SDIV		0

#define		Startup_ARMCLKdiv	0	//	0 :	ARMCLK	= MPLL
									//	1 :	ARMCLK	= MPLL/2
#define		Startup_HCLKdiv		1	//	0 :	HCLK	= ARMCLK
									//	1 :	HCLK	= ARMCLK/2
									//	2 :	HCLK	= ARMCLK/3
									//	3 :	HCLK	= ARMCLK/4
#define		Startup_PCLKdiv		1	//	0 :	PCLK	= HCLK
									//	1 :	PCLK	= HCLK/2

//======================================================================================
//	PORT1 config	[SDRAM_D, DDR] 	or	[SDRAM_L, L2RAM]
//
//	Density			[SDRAM_D, DDR]		0: 256/512/1G
//										1: 128M
//
//					[SDRAM_L, L2RAM]	2: 128M
//										3: 256M
//										4: 512M
//										5: 1G

#define		PORT1_DDR

#define		P1_Density0		3
#define		P1_Density1		3

#define		P1_tREFRESH		780		//	'us' * 100

#define		P1_tRAS			60		//	'ns'
#define		P1_tRC			90		//	'ns'
#define		P1_tRCD			30		//	'ns'
#define		P1_tRP			30		//	'ns'

#define		P1_CL			3


//======================================================================================
//	PORT2 config	[SDRAM_D, DDR] 	or	[SDRAM_L, L2RAM]
//
//	Density			[SDRAM_D, DDR]		0: 256/512/1G
//										1: 128M
//
//					[SDRAM_L, L2RAM]	2: 128M
//										3: 256M
//										4: 512M
//										5: 1G

#define		PORT2_DDR

#define		P2_Density0		3
#define		P2_Density1		3

#define		P2_tREFRESH		780		//	'us' * 100

#define		P2_tRAS			60		//	'ns'
#define		P2_tRC			90		//	'ns'
#define		P2_tRCD			30		//	'ns'
#define		P2_tRP			30		//	'ns'

#define		P2_CL			3



#ifdef __cplusplus
}
#endif

#endif /*__OPTION_H__*/