mmu.c

三星S3C2460 USB DEVICE /USB HOST 监控代码

/*****************************************
 NAME: MMU.C
 DESC: MMU Initialize code
 HISTORY:
 2003.04.04 : ver 0.0
******************************************/

#include "Option.h"
#include "2460addr.h"
#include "2460lib.h"
#include "2460slib.h"
#include "mmu.h"

// 1) Only the section table is used. 
// 2) The cachable/non-cachable area can be changed by MMT_DEFAULT value.
//    The section size is 1MB.



void MMU_Init(void)
{
    int i,j;
    //========================== IMPORTANT NOTE =========================
    //The current stack and code area can't be re-mapped in this routine.
    //If you want memory map mapped freely, your own sophiscated MMU
    //initialization code is needed.
    //===================================================================

    MMU_DisableDCache();
    MMU_DisableICache();
    for(i=0;i<4;i++)
    	for(j=0;j<128;j++)
    	    MMU_CleanInvalidateDCacheSET((i<<30)|(j<<5));
    MMU_InvalidateICache();
    #if 0
    //To complete MMU_Init() fast, Icache may be turned on here.
    MMU_EnableICache(); 
    #endif
    MMU_DisableMMU();
    MMU_InvalidateTLB();

    /*SROM*/
    //MMU_SetMTT(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
    MMU_SetMTT(0x00000000,0x03f00000,0x00000000,RW_CNB);   //SROM Bank0
    MMU_SetMTT(0x04000000,0x07f00000,0x04000000,RW_NCNB);  //SROM Bank1
    MMU_SetMTT(0x08000000,0x0bf00000,0x08000000,RW_CNB);   //SROM Bank2
    //MMU_SetMTT(0x0c000000,0x0c000000,0x0c000000,RW_NCNB);  //Stepping Stone 4KB

    /*Normal SDRAM*/    
    MMU_SetMTT(0x10000000,0x10f00000,0x10000000,RW_CB);    //SDRAM System Group S0-1
    MMU_SetMTT(0x11000000,0x13e00000,0x11000000,RW_NCNB);  //SDRAM System Group S0-2
    MMU_SetMTT(0x13f00000,0x13f00000,0x13f00000,RW_CB);    //SDRAM System Group S0-3

    /*Mobile SDRAM*/    
    MMU_SetMTT(0x20000000,0x21f00000,0x20000000,RW_NCNB);  //SDRAM Image Subsystem Group I0

    /*SFR & Etc*/    
    MMU_SetMTT(0x40000000,0x4a100000,0x40000000,RW_NCNB);  //SFR
    //MMU_SetMTT(0x4a200000,0xfff00000,0x4a200000,RW_FAULT); //not used

    MMU_SetTTBase(_MMUTT_STARTADDRESS);
    MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); 
    	//DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)

    MMU_SetProcessId(0x0);
    MMU_EnableAlignFault();

    MMU_EnableMIDCache();


//Test M&I&D En=========================================
/*
    MMU_EnableMMU();
    MMU_EnableICache();
    MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.    
*/
//===================================================

}    


// attr=RW_CB,RW_CNB,RW_NCNB,RW_FAULT
void ChangeRomCacheStatus(int attr)
{
    int i,j;
    MMU_DisableDCache();
    MMU_DisableICache();
    //If write-back is used,the DCache should be cleared.
    for(i=0;i<4;i++)
    	for(j=0;j<128;j++)
    	    MMU_CleanInvalidateDCacheSET((i<<30)|(j<<5));
    MMU_InvalidateICache();
    MMU_DisableMMU();
    MMU_InvalidateTLB();

    MMU_SetMTT(0x00000000,0x03f00000,0x00000000,attr);   //SROM Bank0
    MMU_SetMTT(0x04000000,0x04f00000,0x04000000,attr);  //SROM Bank1
    MMU_SetMTT(0x05000000,0x05f00000,0x05000000,attr);   //SROM Bank2

    MMU_EnableMMU();
    MMU_EnableICache();
    MMU_EnableDCache();
}    
    

void MMU_SetMTT(unsigned int vaddrStart,unsigned int vaddrEnd,unsigned int paddrStart,unsigned int attr)
{
    unsigned int *pTT;
    unsigned int i,nSec;
    pTT=(unsigned int *)_MMUTT_STARTADDRESS+(vaddrStart>>20);
    nSec=(vaddrEnd>>20)-(vaddrStart>>20);
    for(i=0;i<=nSec;i++)*pTT++=attr |(((paddrStart>>20)+i)<<20);
}