k9s1208.c

三星 s3c2460 从k9f1208u0m NAND FLASH BOOT系统 源代码

#include "option.h"
#include "2460addr.h"
#include "2460lib.h"

#define NF_CMD(cmd)			{rNFCMMD=cmd;}
#define NF_ADDR(addr) 		{rNFADDR=addr;}
#define NF_nFCE_L()			{rNFCONT&=~(1<<7);}
#define NF_nFCE_H()			{rNFCONT|=(1<<7);}
#define NF_RSTECC()			{rNFCONT|=(1<<8);}
#define NF_RDDATA() 			(rNFDATA)
#define NF_WRDATA(data) 	{rNFDATA=data;}
#define NF_TRANSRnB()    		{while(!(rNFSTAT&(1<<13)));} 
#define NF_CLRRnB()    		{(rNFSTAT|=(1<<13));} 
#define NF_MECC_Lock()  		{rNFCONT|=(1<<9);}
#define NF_MECC_UnLock()  	{rNFCONT&=~(1<<9);}


// Minimum timing	TACLS(0ns)+TWRPH0(25ns)+TWRPH1(10ns)+TWH(5ns) >=40ns

#if 1
#define TECH			0x3f
#define TACLS		0
#define TWRPH0		4
#define TWRPH1		0
#else
#define TECH              0x3f
#define TACLS		0  // 0clk(0ns)
#define TWRPH0		1  // 2clk(40ns)
#define TWRPH1		0  // 1clk(20ns)
#endif

void __RdPage512(unsigned char *bufPt); 

int NF_ReadPage(unsigned int block,unsigned int page,unsigned char *buffer)
{
	int i;
	register unsigned char * bufPt=buffer;
	unsigned int blockPage;

	blockPage=(block<<5)+page; 
	NF_RSTECC();    		// Reset ECC
	NF_MECC_UnLock(); 	// Main ECC generation Unlock
	NF_CLRRnB();    		// Clear RnB transition detect
	NF_nFCE_L();      		// nCE enable
    
	NF_CMD(0x00);   		// Read command
    
	//NF_1_Page==512
	// Address 4 cycles
	NF_ADDR(0);	    		// Column address
	NF_ADDR(blockPage&0xff);	    //  page address
	NF_ADDR((blockPage>>8)&0xff);   // 
	NF_ADDR((blockPage>>16)&0xff);  //
	
	NF_TRANSRnB();    		// Wait tRnB(max 12us)


	i=512;
	while(i--!=0)
	{
		*bufPt++=(unsigned char)NF_RDDATA();	// Read one page 
	}

	NF_MECC_Lock(); // Main ECC Generation Lock

#if 1
	rNFMECCDATA0=NF_RDDATA();
	rNFMECCDATA1=NF_RDDATA();
	rNFMECCDATA2=NF_RDDATA();
	rNFMECCDATA3=NF_RDDATA(); //for 24A0 main area ecc3
#endif	 

	NF_nFCE_H();    
	if((rNFESTAT0&0x03)==0x0)   return 1;
	else return 0;

}

int NF_IsBadBlock(unsigned int block)
{
    int i;
    unsigned int blockPage;
    unsigned char data;
    
    
    blockPage=(block<<5);	// For 2'nd cycle I/O[7:5] 

    //  NF_RSTECC();    // Reset ECC
    NF_CLRRnB(); 
    NF_nFCE_L();    
    NF_CMD(0x50);		// Spare array read command
    NF_ADDR(0x5);		// Read the mark of bad block in spare array(M addr=5) 
    NF_ADDR(blockPage&0xff);	// The mark of bad block is in 0 page
    NF_ADDR((blockPage>>8)&0xff);   // For block number A[24:17]
    NF_ADDR((blockPage>>16)&0xff);  // For block number A[25]

   for(i=0;i<10;i++);	// wait tWB(100ns) //?????
    
    NF_TRANSRnB();	// Wait tR(max 12us)
    
    data=(unsigned char)NF_RDDATA();

    NF_nFCE_H();    

    if(data!=0xff)
    {
    	return 1;
    }
    else
    {
    	return 0;
    }
}

void NF_Reset(void)
{
	int i;
   
	NF_nFCE_L();
	NF_CLRRnB();    		// Clear RnB transition detect 
	NF_CMD(0xFF);		//reset command
	for(i=0;i<10;i++);  	//tWB = 100ns. 
	NF_TRANSRnB();   	//wait tRST(not tRnB) 200~500us;
	NF_nFCE_H();
}

void NF_Init(void)
{
     
	rNFCONF=(TECH<<16)|(TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4)|(0<<3)|(0<<2)|(1<<1)|(1<<0);
	//                                                                                             Not support h/w nCE ctl, 8bit, 512B, 4step 
	rNFCONT=(0<<16)|(0<<15)|(0<<14)|(0<<13)|(0<<12)|(0<<11)|(1<<10)|(1<<9)|\
			(0<<8)|(1<<7)|(0<<4)|(0<<3)|(1<<2)|(3<<0);  //????
	//           LdStrAddr   illegalAccINT  LoadINT  StoreINT  RnBINT    TransMode  SpareECCLock MainECCLock
	//            initECC   Reg_nCE  PageSie Lock-tight Lock  Software_mode
	NF_Reset();
}