dram_asm.s

三星 s3c2460 从k9f1208u0m NAND FLASH BOOT系统 源代码

				GET		Option.inc
				GET		2460addr.inc

				EXPORT	InitPORT1
				EXPORT	InitPORT2

				AREA	|C$$code|, CODE, READONLY

InitPORT1		PROC
	[ :DEF: PORT1_SDRAM_D

				ldr		r0,=rPRIORITY1
				ldr		r1,[r0]
				bic		r1,r1,#(0x1<<4)
				str		r1,[r0]					
				
				ldr		r0,=rP1BANKCFG_DDR		;	2nd	:	Issue a PALL command
				ldr		r1,[r0,#0x4]
				bic		r1,r1,#0x3
				orr		r1,r1,#0x1
				str		r1,[r0,#0x4]			

				mov		r1,#0xf					;	3rd	:	Write '0xf' into the refresh timer register.
				str		r1,[r0,#0x8]			

				mov		r1,#0x0					;	4th	:	Wait for a time period equivalent to 120-clock cycles (8 refresh cycles).
SDRAM_loop1		add		r1,r1,#0x1
				cmp		r1,#100
				blt		SDRAM_loop1

				ldr		r1,=(Startup_HCLK/1000)*P1_tREFRESH/100000
				str		r1,[r0,#0x8]			;	5th	:	Program the normal operational value into the refresh timer.

				ldr		r1,[r0]					;	6th	:	Program the MemSelect bits of configuration register.
				bic		r1,r1,#(0x3<<21)
				bic		r1,r1,#(0x1<<0)
				orr		r1,r1,#(0x1<<21)		;	** Set MEMSelect to mSDRAM **
				orr		r1,r1,#(0x1<<0)			;	** Set Databus Width **
				str		r1,[r0]					

				ldr		r1,[r0,#0x4]			;	7th	:	Issue a MRS command
				bic		r1,r1,#0x3
				orr		r1,r1,#0x2
				str		r1,[r0,#0x4]			

				orr		r1,r1,#0x3				;	8th	:	Mobile only) Issue a EMRS command
				str		r1,[r0,#0x4]			

				bic		r1,r1,#0x3				;	9th :	Program the INIT[1:0] to '00b'.
				str		r1,[r0,#0x4]			

				ldr		r1,[r0]					;	10th :	Program the configuration register to their normal operation values.
				ldr		r2,=~(0xfe1fffae)
				and		r1,r1,r2
				orr		r1,r1,#(0x1<<20)		;	** Power Down control **
				orr		r1,r1,#( (((Startup_HCLK/1000*P1_tRAS-1)/1000000)<<16) | (((Startup_HCLK/1000*P1_tRC-1)/1000000)<<12) )
				orr		r1,r1,#( (((Startup_HCLK/1000*P1_tRCD-1)/1000000)<<10) | (((Startup_HCLK/1000*P1_tRP-1)/1000000)<<8) )
				orr		r1,r1,#((P1_Density1<<7)|(P1_Density0<<5)|(P1_CL<<2)|(0x1<<1))	;	** Disable AutoPrecharge **
				str		r1,[r0]

				ldr		r1,[r0,#0x4]
				orr		r1,r1,#((0x1<<6)|(0x1<<2))	;	** Support power save mode, Write buffer enable **
				str		r1,[r0,#0x4]

	]

	[ :DEF: PORT1_DDR 

				ldr		r0,=rPRIORITY1
				ldr		r1,[r0]
				bic		r1,r1,#(0x1<<4)
				str		r1,[r0]

				ldr		r0,=rP1BANKCFG_DDR		;	2nd :	Setting MEMselect and CL area in the Configuration Register0
				ldr		r1,[r0]
				bic		r1,r1,#((0x3<<2)|(0x1<<0))
				orr		r1,r1,#(0x3<<21)				;	** Set MEMSelect to mDDR **
				orr		r1,r1,#((P1_CL<<2)|(0x1<<0))	;	** Set Databus Width **
				str		r1,[r0]				

				ldr		r1,[r0,#0x4]			;	3rd :	Issue a PALL command
				bic		r1,r1,#0x3
				orr		r1,r1,#0x1
				str		r1,[r0,#0x4]		
	
				nop								;	4th :	Wait minimum 2 cycle
				nop
				nop
				nop							

				ldr		r1,[r0]					;	5th :	Program the DLL Enable bit of Control Register0 to low. Issue a EMRS command.
				bic		r1,r1,#(0x1<<24)
				str		r1,[r0]

				ldr		r1,[r0,#0x4]
				orr		r1,r1,#0x3
				str		r1,[r0,#0x4]		
	
				nop								;	6th :	Wait minimum 2 cycle
				nop
				nop
				nop							
	
				ldr		r1,[r0]					;	7th :	Program the DLLReset bit of Control Register0 to high. Issue a MRS command.
				orr		r1,r1,#(0x1<<23)
				str		r1,[r0]
				
				ldr		r1,[r0,#0x4]
				bic		r1,r1,#0x3
				orr		r1,r1,#0x2
				str		r1,[r0,#0x4]		

				nop								;	8th :	Wait minumu 2 cycle
				nop
				nop
				nop							

				ldr		r1,[r0,#0x4]			;	9th :	Issue a PALL command
				bic		r1,r1,#0x3
				orr		r1,r1,#0x1
				str		r1,[r0,#0x4]		

				mov		r1,#0xf					;	10th :	Write '0xf' into the refresh timer register.
				str		r1,[r0,#0x8]		
			
				mov		r1,#0x0					;	11th :	Wait for a time period equivalent to 200-clock cycles (14 refresh cycles).
DDR_loop1		add		r1,r1,#0x1
				cmp		r1,#200
				blt		DDR_loop1

				ldr		r1,[r0]					;	12th :	Program the DLLReset bit of Control Register0 to low. Issue a MRS command.
				bic		r1,r1,#(0x1<<23)
				str		r1,[r0]

				ldr		r1,[r0,#0x4]
				bic		r1,r1,#0x3
				orr		r1,r1,#0x2
				str		r1,[r0,#0x4]

				ldr		r1,=(Startup_HCLK/1000)*P1_tREFRESH/100000
				str		r1,[r0,#0x8]			;	13th :	Program the normal operational value into the refresh timer.

				ldr		r1,[r0,#0x4]			;	14th :	Program the INIT[1:0] to '00b'.
				bic		r1,r1,#0x3
				str		r1,[r0,#0x4]

		[ :DEF: S3C2460X
				ldr		r1,[r0]					;	15th :	Program the configuration register to their normal operation values.
				bic		r1,r1,#((0xf<<16)|(0xf<<12))
				bic		r1,r1,#((0x3<<10)|(0x3<<8))
				orr		r1,r1,#( (((Startup_HCLK/1000)*P1_tRAS/1000000-1)<<16) | (((Startup_HCLK/1000)*P1_tRC/1000000-1)<<12) );
				orr		r1,r1,#( (((Startup_HCLK/1000)*P1_tRCD/1000000-1)<<10) | (((Startup_HCLK/1000)*P1_tRP/1000000-1)<<8) );
				str		r1,[r0]

				ldr		r2,=~(0xfe1000a2)
				and		r1,r1,r2
				orr		r1,r1,#(0<<20)			;	Power Down control
				orr		r1,r1,#((P1_Density1<<7)|(P1_Density0<<5))
				str		r1,[r0]

				ldr		r1,[r0,#0x4]
				bic		r1,r1,#(0x7<<8)
				orr		r1,r1,#(0x3<<8)				;	** DQS delay value. < Reserved for test > **
				bic		r1,r1,#((0x1<<6)|(0x1<<2))
				orr		r1,r1,#((0x1<<6)|(0x0<<2))	;	** Power save mode, Write buffer disable **
				str		r1,[r0,#0x4]				
		]
		[ :DEF: S3C2460A_TMP
				ldr		r1,[r0]					;	15th :	Program the configuration register to their normal operation values.
				ldr		r2,=~(0xfe1fffa2)
				and		r1,r1,r2
				orr		r1,r1,#(0x1<<20)			;	** Power Down control **
				orr		r1,r1,#( (((Startup_HCLK/1000*P1_tRAS-1)/1000000)<<16) | (((Startup_HCLK/1000*P1_tRC-1)/1000000)<<12) )
				orr		r1,r1,#( (((Startup_HCLK/1000*P1_tRCD-1)/1000000)<<10) | (((Startup_HCLK/1000*P1_tRP-1)/1000000)<<8) )
				orr		r1,r1,#((P1_Density1<<7)|(P1_Density0<<5))
				bic		r1,r1,#(0x1<<1)	;	** Enable AutoPrecharge **
				str		r1,[r0]

				ldr		r1,[r0,#0x4]
				bic		r1,r1,#(0x7<<8)
				orr		r1,r1,#(0x3<<8)				;	** DQS delay value. < Reserved for test > **
				bic		r1,r1,#((0x1<<6)|(0x1<<2))
				orr		r1,r1,#((0x1<<6)|(0x1<<2))	;	** Power save mode, Write buffer enable **
				str		r1,[r0,#0x4]
		]
		[ :DEF: S3C2460A
				ldr		r1,[r0]					;	15th :	Program the configuration register to their normal operation values.
				ldr		r2,=~(0xfe1fffa2)
				and		r1,r1,r2
				orr		r1,r1,#(0x1<<20)			;	** Power Down control **
				orr		r1,r1,#( (((Startup_HCLK/1000*P1_tRAS-1)/1000000)<<16) | (((Startup_HCLK/1000*P1_tRC-1)/1000000)<<12) )
				orr		r1,r1,#( (((Startup_HCLK/1000*P1_tRCD-1)/1000000)<<10) | (((Startup_HCLK/1000*P1_tRP-1)/1000000)<<8) )
				orr		r1,r1,#((P1_Density1<<7)|(P1_Density0<<5)|(0x1<<1))	;	** Disable AutoPrecharge **
				str		r1,[r0]

				ldr		r1,[r0,#0x4]
				bic		r1,r1,#(0x7<<8)
				orr		r1,r1,#(0x3<<8)				;	** DQS delay value. < Reserved for test > **
				bic		r1,r1,#((0x1<<6)|(0x1<<2))
				orr		r1,r1,#((0x1<<6)|(0x1<<2))	;	** Power save mode, Write buffer enable **
				str		r1,[r0,#0x4]
		]
		
	]

	[ :DEF: PORT1_SDRAM_L

				ldr		r0,=rPRIORITY1
				ldr		r1,[r0]
				orr		r1,r1,#(0x1<<4)
				str		r1,[r0]					

				ldr		r0,=rP1BANKCFG_L2RAM
				ldr		r1,[r0]					;	2nd	:	Program all registers to their normal operation values.
				bic		r1,r1,#((0xf<<24)|(0xf<<20))
				bic		r1,r1,#((0x3<<18)|(0x3<<16))
				bic		r1,r1,#((0x7<<12)|(0x7<<8))
				bic		r1,r1,#((0x1<<4)|(0x1<<1))
				orr		r1,r1,#( (((Startup_HCLK/1000*P1_tRAS-1)/1000000)<<24) | (((Startup_HCLK/1000*P1_tRC-1)/1000000)<<20) )
				orr		r1,r1,#( (((Startup_HCLK/1000*P1_tRCD-1)/1000000)<<18) | (((Startup_HCLK/1000*P1_tRP-1)/1000000)<<16) )
				orr		r1,r1,#((P1_Density1<<12)|(P1_Density0<<8))
				str		r1,[r0]

				ldr		r1,[r0,#0x4]
				bic		r1,r1,#((0x1<<23)|(0x3<<21)|(0x3<<19)|(0x7<<16))
				bic		r1,r1,#(0x7<<4)
				orr		r1,r1,#(P1_CL<<4)
				str		r1,[r0,#0x4]

				ldr		r1,[r0,#0x8]
				bic		r1,r1,#((0x1<<20)|(0xf<<16))
				bic		r1,r1,#((0x1<<6)|(0x1<<5)|(0x1<<4)|(0x7<<0))
				orr		r1,r1,#((0x1<<6)|(0x0<<5)|(0x1<<4))	; ** Power Down, Auto Precharge, Write buffer **
				orr		r1,r1,#(0x1<<0)
				str		r1,[r0,#0x8]			;	3rd	:	Issue a PALL command

				mov		r1,#0xf					;	4th	:	Write '0xf' into the refresh timer register.
				str		r1,[r0,#0xc]

				mov		r1,#0x0					;	5th	:	Wait for a time period equivalent to 120-clock cycles (8 refresh cycles).
SDRAM_loop1		add		r1,r1,#0x1
				cmp		r1,#100
				blt		SDRAM_loop1

				ldr		r1,=(Startup_HCLK/1000)*P1_tREFRESH/100000
				str		r1,[r0,#0xc]			;	6th	:	Program the normal operational value into the refresh timer.

				ldr		r1,[r0,#0x8]			;	7th	:	Issue a MRS command
				bic		r1,r1,#0x7
				orr		r1,r1,#0x2
				str		r1,[r0,#0x8]

				orr		r1,r1,#0x3				;	8th	:	Mobile only) Issue a EMRS command
				str		r1,[r0,#0x8]

				bic		r1,r1,#0x7				;	9th :	Program the MemoryCommand[2:0] to '000b'.
				str		r1,[r0,#0x8]

	]
	
	[ :DEF: PORT1_L2RAM

				ldr		r0,=rPRIORITY1
				ldr		r1,[r0]
				orr		r1,r1,#(0x1<<4)
				str		r1,[r0]					

				ldr		r0,=rP1BANKCFG_L2RAM
				ldr		r1,[r0]					;	2nd	:	Program all registers to their normal operation values.
				bic		r1,r1,#((0xf<<24)|(0xf<<20))
				bic		r1,r1,#((0x3<<18)|(0x3<<16))
				bic		r1,r1,#((0x7<<12)|(0x7<<8))
				bic		r1,r1,#(0x1<<4)
				orr		r1,r1,#( (((Startup_HCLK/1000*P1_tRAS-1)/1000000)<<24) | (((Startup_HCLK/1000*P1_tRC-1)/1000000)<<20) )
				orr		r1,r1,#( (((Startup_HCLK/1000*P1_tRCD-1)/1000000)<<18) | (((Startup_HCLK/1000*P1_tRP-1)/1000000)<<16) )
				orr		r1,r1,#((P1_Density1<<12)|(P1_Density0<<8))
				orr		r1,r1,#(0x1<<1)
				str		r1,[r0]

				ldr		r1,[r0,#0x4]
				bic		r1,r1,#((0x1<<23)|(0x3<<21)|(0x3<<19)|(0x7<<16))
				bic		r1,r1,#(0x7<<4)
				orr		r1,r1,#(P1_CL<<4)
				str		r1,[r0,#0x4]

				ldr		r1,[r0,#0x8]
				bic		r1,r1,#((0x1<<20)|(0xf<<16))
				bic		r1,r1,#(0x7<<10)
				bic		r1,r1,#((0x1<<6)|(0x1<<5)|(0x1<<4)|(0x7<<0))
				orr		r1,r1,#(0x4<<10)					; ** DQS delay value. < Reserved for test > **
				orr		r1,r1,#((0x1<<6)|(0x0<<5)|(0x1<<4))	; ** Power Down, Auto Precharge, Write buffer **
				orr		r1,r1,#(0x1<<0)
				str		r1,[r0,#0x8]			;	3rd	:	Issue a PALL command

				mov		r1,#0xf					;	4th	:	Write '0xf' into the refresh timer register.
				str		r1,[r0,#0xc]

				mov		r1,#0x0					;	5th	:	Wait for a time period equivalent to 120-clock cycles (8 refresh cycles).
L2RAM_loop1		add		r1,r1,#0x1
				cmp		r1,#100
				blt		L2RAM_loop1

				ldr		r1,=(Startup_HCLK/1000)*P1_tREFRESH/100000
				str		r1,[r0,#0xc]			;	6th	:	Program the normal operational value into the refresh timer.

				ldr		r1,[r0,#0x8]			;	7th	:	Issue a MRS command
				bic		r1,r1,#0x7
				orr		r1,r1,#0x2
				str		r1,[r0,#0x8]

				orr		r1,r1,#0x3				;	8th	:	Mobile only) Issue a EMRS command
				str		r1,[r0,#0x8]

				bic		r1,r1,#0x7				;	9th :	Program the MemoryCommand[2:0] to '000b'.
				str		r1,[r0,#0x8]
	]

				bx		lr