lpc2368.s

基于ARM的单片机读写U盘文件（ADS)

;import symbols
	IMPORT  __main
	IMPORT  __use_two_region_memory
;export symbols
 	EXPORT  Reset_Handler
 	EXPORT  __user_initial_stackheap
 
 
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
USR_Mode        EQU     0x10
FIQ_Mode        EQU     0x11
IRQ_Mode        EQU     0x12
SVC_Mode        EQU     0x13
ABT_Mode        EQU     0x17
UND_Mode        EQU     0x1B
SYS_Mode        EQU     0x1F
IRQ_Bit         EQU     0x80            ; when I bit is set, IRQ is disabled
FRQ_Bit         EQU     0x40            ; when F bit is set, FIQ is disabled

UND_Stack_Size  EQU     0x00000000
SVC_Stack_Size  EQU     0x00000100
ABT_Stack_Size  EQU     0x00000000
FIQ_Stack_Size  EQU     0x00000000
IRQ_Stack_Size  EQU     0x00000400		;12-13日更改
USR_Stack_Size  EQU     0x00000B00		;12-13日更改




; System Control Block (SCB) Module Definitions
SCB_BASE        EQU     0xE01FC000      ; SCB Base Address
PLLCON_OFS      EQU     0x80            ; PLL Control Offset
PLLCFG_OFS      EQU     0x84            ; PLL Configuration Offset
PLLSTAT_OFS     EQU     0x88            ; PLL Status Offset
PLLFEED_OFS     EQU     0x8C            ; PLL Feed Offset
CCLKCFG_OFS     EQU     0x104           ; CPU Clock Divider Reg Offset
USBCLKCFG_OFS   EQU     0x108           ; USB Clock Divider Reg Offset
CLKSRCSEL_OFS   EQU     0x10C           ; Clock Source Sel Reg Offset
SCS_OFS         EQU     0x1A0           ; Sys Control and Status Reg Offset
PCLKSEL0_OFS    EQU     0x1A8           ; Periph Clock Sel Reg 0 Offset
PCLKSEL1_OFS    EQU     0x1AC           ; Periph Clock Sel Reg 0 Offset


OSCRANGE        EQU     (1<<4)          ; Oscillator Range Select
OSCEN           EQU     (1<<5)          ; Main oscillator Enable
OSCSTAT         EQU     (1<<6)          ; Main Oscillator Status
PLLCON_PLLE     EQU     (1<<0)          ; PLL Enable
PLLCON_PLLC     EQU     (1<<1)          ; PLL Connect
PLLSTAT_M       EQU     (0x7FFF<<0)     ; PLL M Value
PLLSTAT_N       EQU     (0xFF<<16)      ; PLL N Value
PLLSTAT_PLOCK   EQU     (1<<26)         ; PLL Lock Status


CLOCK_SETUP     EQU     1
SCS_Val         EQU     0x00000021
CLKSRCSEL_Val   EQU     0x00000001
PLLCFG_Val      EQU     0x0000000B
CCLKCFG_Val     EQU     0x00000003
USBCLKCFG_Val   EQU     0x00000005
PCLKSEL0_Val    EQU     0x00000000
PCLKSEL1_Val    EQU     0x00000000


; Memory Accelerator Module (MAM) definitions
MAM_BASE        EQU     0xE01FC000      ; MAM Base Address
MAMCR_OFS       EQU     0x00            ; MAM Control Offset
MAMTIM_OFS      EQU     0x04            ; MAM Timing Offset


MAM_SETUP       EQU     1
MAMCR_Val       EQU     0x00000001
MAMTIM_Val      EQU     0x00000004

REMAP           EQU		1
MEMMAP          EQU     0xE01FC040      ; Memory Mapping Control


PINSEL_BASE	    EQU    0xE002C000
PINSEL10_OFS	EQU	   0x28
PINSEL10_Val	EQU	   0

Stack_Size      EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
                         FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size)

                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem       SPACE   Stack_Size

Stack_Top       EQU     Stack_Mem + Stack_Size
Heap_Size       EQU     0x00000000

                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
Heap_Mem        SPACE   Heap_Size
; Area Definition and Entry Point
;  Startup Code must be linked first at Address at which it expects to run.
				
				CODE32
                AREA    RESET, CODE, READONLY
                ENTRY


; Exception Vectors
;  Mapped to Address 0.
;  Absolute addressing mode must be used.
;  Dummy Handlers are implemented as infinite loops which can be modified.

Vectors         LDR     PC, Reset_Addr         
                LDR     PC, Undef_Addr
                LDR     PC, SWI_Addr
                LDR     PC, PAbt_Addr
                LDR     PC, DAbt_Addr
                DCD     0xb9206e50                            ; Reserved Vector 
                LDR     PC, [PC, #-0x0120]     ; Vector from VicVectAddr
                LDR     PC, FIQ_Addr

Reset_Addr      DCD     Reset_Handler
Undef_Addr      DCD     Undef_Handler
SWI_Addr        DCD     SWI_Handler
PAbt_Addr       DCD     PAbt_Handler
DAbt_Addr       DCD     DAbt_Handler
                DCD     0                      ; Reserved Address 
IRQ_Addr        DCD     IRQ_Handler
FIQ_Addr        DCD     FIQ_Handler

Undef_Handler   B       Undef_Handler
PAbt_Handler    B       PAbt_Handler
DAbt_Handler    B       DAbt_Handler
IRQ_Handler     B       IRQ_Handler
FIQ_Handler     B       FIQ_Handler


SWI_Handler     
;//增加开/关中断处理 TY-2007-10-20                                 
       	CMP     R0, #4
       	LDRLO   PC, [PC, R0, LSL #2]
       	MOVS    PC, LR

SwiFunction
       	DCD    	IRQDisable   ;0
       	DCD		IRQEnable    ;1
       	DCD		FIQDisable	 ;2
       	DCD		FIQEnable	 ;3

IRQDisable
       ;关IRQ中断
       	MRS     R0, SPSR
       	ORR     R0, R0, #IRQ_Bit 
       	MSR     SPSR_c, R0
       	MOVS    PC, LR

IRQEnable
       	;开IRQ中断
       	MRS   	R0, SPSR
       	BIC   	R0, R0, #IRQ_Bit 
       	MSR   	SPSR_c, R0
		MOVS    PC, LR
        
FIQDisable
       ;关FIQ中断
       	MSR		CPSR_c, #(SVC_Mode|FRQ_Bit)
       	MRS     R0, SPSR
       	ORR     R0, R0, #FRQ_Bit
       	MSR     SPSR_c, R0
       	MOVS    PC, LR

FIQEnable
       ;开FIQ中断
		MSR	CPSR_c, #(SVC_Mode|FRQ_Bit)
       	MRS  	R0, SPSR
       	BIC   	R0, R0, #FRQ_Bit
      	MSR   	SPSR_c, R0
       	MOVS  	PC, LR
;// Changed 2007-10-20

Reset_Handler   
		BL	INIT_TARGET
		BL	INIT_STACK
		
INIT_TARGET	
;Setup Clock
        IF      CLOCK_SETUP != 0
        LDR     R0, =SCB_BASE
        MOV     R1, #0xAA
        MOV     R2, #0x55

;Configure and Enable PLL
        LDR     R3, =SCS_Val          ; Enable main oscillator
        STR     R3, [R0, #SCS_OFS] 

        IF      (SCS_Val:AND:OSCEN) != 0  
OSC_Loop        LDR     R3, [R0, #SCS_OFS]    ; Wait for main osc stabilize
        ANDS    R3, R3, #OSCSTAT
        BEQ     OSC_Loop
        ENDIF

        LDR     R3, =CLKSRCSEL_Val    ; Select PLL source clock
        STR     R3, [R0, #CLKSRCSEL_OFS] 
        LDR     R3, =PLLCFG_Val
        STR     R3, [R0, #PLLCFG_OFS] 
        STR     R1, [R0, #PLLFEED_OFS]
        STR     R2, [R0, #PLLFEED_OFS]
        MOV     R3, #PLLCON_PLLE
        STR     R3, [R0, #PLLCON_OFS]
        STR     R1, [R0, #PLLFEED_OFS]
        STR     R2, [R0, #PLLFEED_OFS]

;  Wait until PLL Locked
PLL_Loop        LDR     R3, [R0, #PLLSTAT_OFS]
        ANDS    R3, R3, #PLLSTAT_PLOCK
        BEQ     PLL_Loop

M_N_Lock        LDR     R3, [R0, #PLLSTAT_OFS]
        LDR     R4, =(PLLSTAT_M:OR:PLLSTAT_N)
        AND     R3, R3, R4
        LDR     R4, =PLLCFG_Val
        EORS    R3, R3, R4
        BNE     M_N_Lock

;Setup CPU clock divider
        MOV     R3, #CCLKCFG_Val
        STR     R3, [R0, #CCLKCFG_OFS]

;Setup USB clock divider
        LDR     R3, =USBCLKCFG_Val
        STR     R3, [R0, #USBCLKCFG_OFS]

;Setup Peripheral Clock
        LDR     R3, =PCLKSEL0_Val
        STR     R3, [R0, #PCLKSEL0_OFS]
        LDR     R3, =PCLKSEL1_Val
        STR     R3, [R0, #PCLKSEL1_OFS]

;Switch to PLL Clock
        MOV     R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
        STR     R3, [R0, #PLLCON_OFS]
        STR     R1, [R0, #PLLFEED_OFS]
        STR     R2, [R0, #PLLFEED_OFS]
        ENDIF   ; CLOCK_SETUP


;Setup MAM
        IF      MAM_SETUP != 0
        LDR     R0, =MAM_BASE
        MOV     R1, #MAMTIM_Val
        STR     R1, [R0, #MAMTIM_OFS] 
        MOV     R1, #MAMCR_Val
        STR     R1, [R0, #MAMCR_OFS] 
        ENDIF   ; MAM_SETUP


; Memory Mapping (when Interrupt Vectors are in RAM)
        IF      REMAP != 0
        LDR     R0, =MEMMAP
        MOV     R1, #1
        STR     R1, [R0]
        ENDIF
        
;Pinsel10=0       
        LDR     R0, =PINSEL_BASE
        LDR     R3, =PINSEL10_Val         ; Enable main oscillator
        STR     R3, [R0, #PINSEL10_OFS] 
        
INIT_STACK       
; Setup Stack for each mode
        LDR     R0, =Stack_Top;for IAP

;  Enter Undefined Instruction Mode and set its Stack Pointer
        MSR     CPSR_c, #UND_Mode:OR:IRQ_Bit:OR:FRQ_Bit
        MOV     SP, R0
        SUB     R0, R0, #UND_Stack_Size

;  Enter Abort Mode and set its Stack Pointer
        MSR     CPSR_c, #ABT_Mode:OR:IRQ_Bit:OR:FRQ_Bit
        MOV     SP, R0
        SUB     R0, R0, #ABT_Stack_Size

;  Enter FIQ Mode and set its Stack Pointer
        MSR     CPSR_c, #FIQ_Mode:OR:IRQ_Bit:OR:FRQ_Bit
        MOV     SP, R0
        SUB     R0, R0, #FIQ_Stack_Size

;  Enter IRQ Mode and set its Stack Pointer
        MSR     CPSR_c, #IRQ_Mode:OR:IRQ_Bit:OR:FRQ_Bit
        MOV     SP, R0
        SUB     R0, R0, #IRQ_Stack_Size

;  Enter Supervisor Mode and set its Stack Pointer
        MSR     CPSR_c, #SVC_Mode:OR:IRQ_Bit:OR:FRQ_Bit
        MOV     SP, R0
        SUB     R0, R0, #SVC_Stack_Size

;  Enter User Mode and set its Stack Pointer
		
		MSR     CPSR_c, #USR_Mode
        MOV     SP, R0
        SUB     SL, SP, #USR_Stack_Size


; Enter the C code
         B       __main



; User Initial Stack & Heap
        AREA    |.text|, CODE, READONLY
__user_initial_stackheap

        LDR     R0, =  Heap_Mem
        ;LDR     R1, =(Stack_Mem + USR_Stack_Size)
        LDR     R1, =Stack_Mem + USR_Stack_Size
        LDR     R2, = (Heap_Mem +      Heap_Size)
        LDR     R3, = Stack_Mem
        BX      LR


        END