qdq.map.qmsg

八路抢答器设计 源码 功能模块设计 带电路图

{ "Warning" "WSGN_SEARCH_FILE" "lpm_counter0.tdf 1 1 " "Warning: Using design file lpm_counter0.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter0 " "Info: Found entity 1: lpm_counter0" {  } { { "lpm_counter0.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/TEST/lpm_counter0.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter0 lpm_counter0:inst3 " "Info: Elaborating entity \"lpm_counter0\" for hierarchy \"lpm_counter0:inst3\"" {  } { { "qdq.bdf" "inst3" { Schematic "C:/Documents and Settings/Administrator/桌面/TEST/qdq.bdf" { { 240 -280 -136 320 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter0:inst3\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter0:inst3\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.tdf" "lpm_counter_component" { Text "C:/Documents and Settings/Administrator/桌面/TEST/lpm_counter0.tdf" 45 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter0:inst3\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"lpm_counter0:inst3\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/TEST/lpm_counter0.tdf" 45 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_75i.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_75i.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_75i " "Info: Found entity 1: cntr_75i" {  } { { "db/cntr_75i.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/TEST/db/cntr_75i.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_75i lpm_counter0:inst3\|lpm_counter:lpm_counter_component\|cntr_75i:auto_generated " "Info: Elaborating entity \"cntr_75i\" for hierarchy \"lpm_counter0:inst3\|lpm_counter:lpm_counter_component\|cntr_75i:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_counter1.vhd 2 1 " "Warning: Using design file lpm_counter1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_counter1-SYN " "Info: Found design unit 1: lpm_counter1-SYN" {  } { { "lpm_counter1.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/TEST/lpm_counter1.vhd" 48 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter1 " "Info: Found entity 1: lpm_counter1" {  } { { "lpm_counter1.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/TEST/lpm_counter1.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter1 lpm_counter1:inst37 " "Info: Elaborating entity \"lpm_counter1\" for hierarchy \"lpm_counter1:inst37\"" {  } { { "qdq.bdf" "inst37" { Schematic "C:/Documents and Settings/Administrator/桌面/TEST/qdq.bdf" { { 600 -312 -248 744 "inst37" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter1:inst37\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter1:inst37\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter1.vhd" "lpm_counter_component" { Text "C:/Documents and Settings/Administrator/桌面/TEST/lpm_counter1.vhd" 70 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter1:inst37\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"lpm_counter1:inst37\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter1.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/TEST/lpm_counter1.vhd" 70 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_lkh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_lkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_lkh " "Info: Found entity 1: cntr_lkh" {  } { { "db/cntr_lkh.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/TEST/db/cntr_lkh.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_lkh lpm_counter1:inst37\|lpm_counter:lpm_counter_component\|cntr_lkh:auto_generated " "Info: Elaborating entity \"cntr_lkh\" for hierarchy \"lpm_counter1:inst37\|lpm_counter:lpm_counter_component\|cntr_lkh:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_CREATED_ALOAD_CCT" "" "Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." { { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74192:inst14\|25 74192:inst14\|25~\$emulated 74192:inst14\|25~8 " "Info: Register \"74192:inst14\|25\" converted into equivalent circuit using register \"74192:inst14\|25~\$emulated\" and latch \"74192:inst14\|25~8\"" {  } { { "74192.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74192.bdf" { { 320 792 856 400 "25" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74192:inst14\|23 74192:inst14\|23~\$emulated 74192:inst14\|23~8 " "Info: Register \"74192:inst14\|23\" converted into equivalent circuit using register \"74192:inst14\|23~\$emulated\" and latch \"74192:inst14\|23~8\"" {  } { { "74192.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74192.bdf" { { 808 792 856 888 "23" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74192:inst14\|26 74192:inst14\|26~\$emulated 74192:inst14\|26~8 " "Info: Register \"74192:inst14\|26\" converted into equivalent circuit using register \"74192:inst14\|26~\$emulated\" and latch \"74192:inst14\|26~8\"" {  } { { "74192.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74192.bdf" { { 80 792 856 160 "26" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74192:inst14\|24 74192:inst14\|24~\$emulated 74192:inst14\|24~8 " "Info: Register \"74192:inst14\|24\" converted into equivalent circuit using register \"74192:inst14\|24~\$emulated\" and latch \"74192:inst14\|24~8\"" {  } { { "74192.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74192.bdf" { { 560 792 856 640 "24" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74192:inst15\|25 74192:inst15\|25~\$emulated 74192:inst15\|25~8 " "Info: Register \"74192:inst15\|25\" converted into equivalent circuit using register \"74192:inst15\|25~\$emulated\" and latch \"74192:inst15\|25~8\"" {  } { { "74192.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74192.bdf" { { 320 792 856 400 "25" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74192:inst15\|23 74192:inst15\|23~\$emulated 74192:inst15\|23~8 " "Info: Register \"74192:inst15\|23\" converted into equivalent circuit using register \"74192:inst15\|23~\$emulated\" and latch \"74192:inst15\|23~8\"" {  } { { "74192.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74192.bdf" { { 808 792 856 888 "23" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74192:inst15\|26 74192:inst15\|26~\$emulated 74192:inst15\|26~8 " "Info: Register \"74192:inst15\|26\" converted into equivalent circuit using register \"74192:inst15\|26~\$emulated\" and latch \"74192:inst15\|26~8\"" {  } { { "74192.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74192.bdf" { { 80 792 856 160 "26" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "74192:inst15\|24 74192:inst15\|24~\$emulated 74192:inst15\|24~8 " "Info: Register \"74192:inst15\|24\" converted into equivalent circuit using register \"74192:inst15\|24~\$emulated\" and latch \"74192:inst15\|24~8\"" {  } { { "74192.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74192.bdf" { { 560 792 856 640 "24" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0}  } {  } 0 0 "Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "138 " "Info: Implemented 138 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "18 " "Info: Implemented 18 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "23 " "Info: Implemented 23 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "97 " "Info: Implemented 97 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 12 13:59:46 2007 " "Info: Processing ended: Wed Dec 12 13:59:46 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}