📄 qdq.map.rpt
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; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 26 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; cntr_75i ; Untyped ;
+------------------------+-------------+------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_counter1:inst37|lpm_counter:lpm_counter_component ;
+------------------------+-------------+-------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+-------------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 1 ; Integer ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; cntr_lkh ; Untyped ;
+------------------------+-------------+-------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
Info: Processing started: Wed Dec 12 13:59:43 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off qdq -c qdq
Info: Found 1 design units, including 1 entities, in source file qdq.bdf
Info: Found entity 1: qdq
Info: Elaborating entity "qdq" for the top level hierarchy
Warning: Block or symbol "NOT" of instance "inst27" overlaps another block or symbol
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/others/maxplus2/7448.bdf
Info: Found entity 1: 7448
Info: Elaborating entity "7448" for hierarchy "7448:inst2"
Info: Elaborated megafunction instantiation "7448:inst2"
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/others/maxplus2/74279.bdf
Info: Found entity 1: 74279
Info: Elaborating entity "74279" for hierarchy "74279:inst1"
Info: Elaborated megafunction instantiation "74279:inst1"
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/others/maxplus2/74148.bdf
Info: Found entity 1: 74148
Info: Elaborating entity "74148" for hierarchy "74148:inst"
Info: Elaborated megafunction instantiation "74148:inst"
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/others/maxplus2/74192.bdf
Info: Found entity 1: 74192
Info: Elaborating entity "74192" for hierarchy "74192:inst15"
Info: Elaborated megafunction instantiation "74192:inst15"
Warning: Using design file lpm_counter0.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: lpm_counter0
Info: Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:inst3"
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:inst3|lpm_counter:lpm_counter_component"
Info: Elaborated megafunction instantiation "lpm_counter0:inst3|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_75i.tdf
Info: Found entity 1: cntr_75i
Info: Elaborating entity "cntr_75i" for hierarchy "lpm_counter0:inst3|lpm_counter:lpm_counter_component|cntr_75i:auto_generated"
Warning: Using design file lpm_counter1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: lpm_counter1-SYN
Info: Found entity 1: lpm_counter1
Info: Elaborating entity "lpm_counter1" for hierarchy "lpm_counter1:inst37"
Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter1:inst37|lpm_counter:lpm_counter_component"
Info: Elaborated megafunction instantiation "lpm_counter1:inst37|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_lkh.tdf
Info: Found entity 1: cntr_lkh
Info: Elaborating entity "cntr_lkh" for hierarchy "lpm_counter1:inst37|lpm_counter:lpm_counter_component|cntr_lkh:auto_generated"
Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state.
Info: Register "74192:inst14|25" converted into equivalent circuit using register "74192:inst14|25~$emulated" and latch "74192:inst14|25~8"
Info: Register "74192:inst14|23" converted into equivalent circuit using register "74192:inst14|23~$emulated" and latch "74192:inst14|23~8"
Info: Register "74192:inst14|26" converted into equivalent circuit using register "74192:inst14|26~$emulated" and latch "74192:inst14|26~8"
Info: Register "74192:inst14|24" converted into equivalent circuit using register "74192:inst14|24~$emulated" and latch "74192:inst14|24~8"
Info: Register "74192:inst15|25" converted into equivalent circuit using register "74192:inst15|25~$emulated" and latch "74192:inst15|25~8"
Info: Register "74192:inst15|23" converted into equivalent circuit using register "74192:inst15|23~$emulated" and latch "74192:inst15|23~8"
Info: Register "74192:inst15|26" converted into equivalent circuit using register "74192:inst15|26~$emulated" and latch "74192:inst15|26~8"
Info: Register "74192:inst15|24" converted into equivalent circuit using register "74192:inst15|24~$emulated" and latch "74192:inst15|24~8"
Info: Implemented 138 device resources after synthesis - the final resource count might be different
Info: Implemented 18 input pins
Info: Implemented 23 output pins
Info: Implemented 97 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Processing ended: Wed Dec 12 13:59:46 2007
Info: Elapsed time: 00:00:04
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