qdq.tan.rpt

八路抢答器设计 源码 功能模块设计 带电路图

; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; pin_name12      ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; zcrinput        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name1       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name6       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name4       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name7       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name5       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name3       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name0       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name2       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name13      ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name14      ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name15      ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name8       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name10      ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name11      ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; pin_name9       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pin_name12'                                                                                                                                                                                                    ;
+-------+------------------------------------------------+---------------------------+---------------------------+------------+------------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                      ; To                        ; From Clock ; To Clock   ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------------------+---------------------------+------------+------------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name12 ; pin_name12 ; None                        ; None                      ; 0.407 ns                ;
+-------+------------------------------------------------+---------------------------+---------------------------+------------+------------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'zcrinput'                                                                                                                                                                                                                                                                                                                                ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                    ; To                                                                                      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 50.01 MHz ( period = 19.995 ns )               ; 74192:inst15|25~$emulated                                                               ; 74192:inst15|25~$emulated                                                               ; zcrinput   ; zcrinput ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; 56.54 MHz ( period = 17.686 ns )               ; 74192:inst15|26~$emulated                                                               ; 74192:inst15|26~$emulated                                                               ; zcrinput   ; zcrinput ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; 73.22 MHz ( period = 13.657 ns )               ; 74192:inst14|25~$emulated                                                               ; 74192:inst14|25~$emulated                                                               ; zcrinput   ; zcrinput ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; 130.99 MHz ( period = 7.634 ns )               ; lpm_counter1:inst37|lpm_counter:lpm_counter_component|cntr_lkh:auto_generated|safe_q[0] ; lpm_counter1:inst37|lpm_counter:lpm_counter_component|cntr_lkh:auto_generated|safe_q[0] ; zcrinput   ; zcrinput ; None                        ; None                      ; 0.803 ns                ;
; N/A   ; 138.16 MHz ( period = 7.238 ns )               ; 74192:inst14|26~$emulated                                                               ; 74192:inst14|26~$emulated                                                               ; zcrinput   ; zcrinput ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; 323.94 MHz ( period = 3.087 ns )               ; 74192:inst15|23~$emulated                                                               ; 74192:inst15|23~$emulated                                                               ; zcrinput   ; zcrinput ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; 74192:inst14|23~$emulated                                                               ; 74192:inst14|23~$emulated                                                               ; zcrinput   ; zcrinput ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; 74192:inst15|24~$emulated                                                               ; 74192:inst15|24~$emulated                                                               ; zcrinput   ; zcrinput ; None                        ; None                      ; 0.407 ns                ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+