qdq.tan.rpt

八路抢答器设计 源码 功能模块设计 带电路图

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programming logic devices manufactured by Altera and sold by 
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                   ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+---------------------------+---------------------------+------------+------------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                                    ; From                      ; To                        ; From Clock ; To Clock   ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+---------------------------+---------------------------+------------+------------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 6.171 ns                                       ; pin_name13                ; 74192:inst15|25~8         ; --         ; zcrinput   ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 34.037 ns                                      ; 74192:inst15|25~$emulated ; pin_name16                ; zcrinput   ; --         ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 14.951 ns                                      ; pin_name7                 ; pin_name16                ; --         ; --         ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 20.478 ns                                      ; zcrinput                  ; 74192:inst15|25~$emulated ; --         ; zcrinput   ; 0            ;
; Clock Setup: 'zcrinput'      ; N/A                                      ; None          ; 50.01 MHz ( period = 19.995 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; zcrinput   ; zcrinput   ; 0            ;
; Clock Setup: 'pin_name13'    ; N/A                                      ; None          ; 50.78 MHz ( period = 19.691 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name13 ; pin_name13 ; 0            ;
; Clock Setup: 'pin_name10'    ; N/A                                      ; None          ; 57.99 MHz ( period = 17.245 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name10 ; pin_name10 ; 0            ;
; Clock Setup: 'pin_name14'    ; N/A                                      ; None          ; 61.38 MHz ( period = 16.291 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name14 ; pin_name14 ; 0            ;
; Clock Setup: 'pin_name11'    ; N/A                                      ; None          ; 68.12 MHz ( period = 14.680 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name11 ; pin_name11 ; 0            ;
; Clock Setup: 'pin_name15'    ; N/A                                      ; None          ; 69.90 MHz ( period = 14.307 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name15 ; pin_name15 ; 0            ;
; Clock Setup: 'clock'         ; N/A                                      ; None          ; 85.90 MHz ( period = 11.641 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; clock      ; clock      ; 0            ;
; Clock Setup: 'pin_name2'     ; N/A                                      ; None          ; 103.92 MHz ( period = 9.623 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name2  ; pin_name2  ; 0            ;
; Clock Setup: 'pin_name0'     ; N/A                                      ; None          ; 103.92 MHz ( period = 9.623 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name0  ; pin_name0  ; 0            ;
; Clock Setup: 'pin_name3'     ; N/A                                      ; None          ; 103.92 MHz ( period = 9.623 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name3  ; pin_name3  ; 0            ;
; Clock Setup: 'pin_name5'     ; N/A                                      ; None          ; 103.92 MHz ( period = 9.623 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name5  ; pin_name5  ; 0            ;
; Clock Setup: 'pin_name7'     ; N/A                                      ; None          ; 103.92 MHz ( period = 9.623 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name7  ; pin_name7  ; 0            ;
; Clock Setup: 'pin_name4'     ; N/A                                      ; None          ; 103.92 MHz ( period = 9.623 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name4  ; pin_name4  ; 0            ;
; Clock Setup: 'pin_name6'     ; N/A                                      ; None          ; 103.92 MHz ( period = 9.623 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name6  ; pin_name6  ; 0            ;
; Clock Setup: 'pin_name1'     ; N/A                                      ; None          ; 103.92 MHz ( period = 9.623 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name1  ; pin_name1  ; 0            ;
; Clock Setup: 'pin_name8'     ; N/A                                      ; None          ; 162.39 MHz ( period = 6.158 ns )               ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name8  ; pin_name8  ; 0            ;
; Clock Setup: 'pin_name9'     ; N/A                                      ; None          ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name9  ; pin_name9  ; 0            ;
; Clock Setup: 'pin_name12'    ; N/A                                      ; None          ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name12 ; pin_name12 ; 0            ;
; Clock Hold: 'zcrinput'       ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~8         ; 74192:inst15|25~$emulated ; zcrinput   ; zcrinput   ; 14           ;
; Clock Hold: 'pin_name13'     ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name13 ; pin_name13 ; 6            ;
; Clock Hold: 'pin_name10'     ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name10 ; pin_name10 ; 5            ;
; Clock Hold: 'pin_name14'     ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name14 ; pin_name14 ; 5            ;
; Clock Hold: 'pin_name11'     ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name11 ; pin_name11 ; 3            ;
; Clock Hold: 'pin_name15'     ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name15 ; pin_name15 ; 3            ;
; Clock Hold: 'clock'          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; clock      ; clock      ; 5            ;
; Clock Hold: 'pin_name1'      ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name1  ; pin_name1  ; 3            ;
; Clock Hold: 'pin_name6'      ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name6  ; pin_name6  ; 3            ;
; Clock Hold: 'pin_name4'      ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name4  ; pin_name4  ; 3            ;
; Clock Hold: 'pin_name7'      ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name7  ; pin_name7  ; 3            ;
; Clock Hold: 'pin_name5'      ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name5  ; pin_name5  ; 3            ;
; Clock Hold: 'pin_name3'      ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name3  ; pin_name3  ; 3            ;
; Clock Hold: 'pin_name0'      ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name0  ; pin_name0  ; 3            ;
; Clock Hold: 'pin_name2'      ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name2  ; pin_name2  ; 3            ;
; Clock Hold: 'pin_name8'      ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name8  ; pin_name8  ; 2            ;
; Clock Hold: 'pin_name9'      ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; 74192:inst15|25~$emulated ; 74192:inst15|25~$emulated ; pin_name9  ; pin_name9  ; 1            ;
; Total number of failed paths ;                                          ;               ;                                                ;                           ;                           ;            ;            ; 68           ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+---------------------------+---------------------------+------------+------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;