qdq.tan.rpt

八路抢答器设计 源码 功能模块设计 带电路图

Timing Analyzer report for qdq
Wed Dec 12 14:00:22 2007
Version 6.0 Build 178 04/27/2006 SJ Web Edition


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; Table of Contents ;
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  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'pin_name12'
  6. Clock Setup: 'zcrinput'
  7. Clock Setup: 'pin_name1'
  8. Clock Setup: 'pin_name6'
  9. Clock Setup: 'pin_name4'
 10. Clock Setup: 'pin_name7'
 11. Clock Setup: 'pin_name5'
 12. Clock Setup: 'pin_name3'
 13. Clock Setup: 'pin_name0'
 14. Clock Setup: 'pin_name2'
 15. Clock Setup: 'pin_name13'
 16. Clock Setup: 'pin_name14'
 17. Clock Setup: 'pin_name15'
 18. Clock Setup: 'pin_name8'
 19. Clock Setup: 'pin_name10'
 20. Clock Setup: 'pin_name11'
 21. Clock Setup: 'clock'
 22. Clock Setup: 'pin_name9'
 23. Clock Hold: 'zcrinput'
 24. Clock Hold: 'pin_name1'
 25. Clock Hold: 'pin_name6'
 26. Clock Hold: 'pin_name4'
 27. Clock Hold: 'pin_name7'
 28. Clock Hold: 'pin_name5'
 29. Clock Hold: 'pin_name3'
 30. Clock Hold: 'pin_name0'
 31. Clock Hold: 'pin_name2'
 32. Clock Hold: 'pin_name13'
 33. Clock Hold: 'pin_name14'
 34. Clock Hold: 'pin_name15'
 35. Clock Hold: 'pin_name8'
 36. Clock Hold: 'pin_name10'
 37. Clock Hold: 'pin_name11'
 38. Clock Hold: 'clock'
 39. Clock Hold: 'pin_name9'
 40. tsu
 41. tco
 42. tpd
 43. th
 44. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License