新建 文本文档.txt

摘抄的主要是为了获得资源

移位寄存器
module shft_reg (CLR , SET , DIR , CE , LOAD , DATA , SI , data_out , CLK );
input CLR , SET , CE , LOAD , DIR , SI , CLK ;
input [3:0] DATA ;
output [3:0] data_out ;

reg [3:0] TEMP;

	always @(posedge CLK )
	begin
		if (CE == 1'b1)
			if (CLR == 1'b1)
				TEMP = {4{1'b0}};
			else if (SET == 1'b1)
				TEMP = {4{1'b1}};
			else if (LOAD == 1'b1)
				TEMP = DATA ;
			else if (DIR == 1'b1)
				TEMP = {SI , TEMP [3:1]};
			else
				TEMP = {TEMP [2:0], SI };
	end

        assign data_out = TEMP;
endmodule

二进制到BCD
module bin2bcd (data_in ,EN ,data_out );

input [3:0] data_in ;
input EN ;
output [7:0] data_out ;
reg [7:0] data_out ;

	always @(data_in or EN )
	begin
		data_out = {8{1'b0}};
		if (EN == 1)
		begin
			case (data_in [3:1]) 
				3'b000 : data_out [7:1] = 7'b0000000;
				3'b001 : data_out [7:1] = 7'b0000001;
				3'b010 : data_out [7:1] = 7'b0000010;
				3'b011 : data_out [7:1] = 7'b0000011;
				3'b100 : data_out [7:1] = 7'b0000100;
				3'b101 : data_out [7:1] = 7'b0001000;
				3'b110 : data_out [7:1] = 7'b0001001;
				3'b111 : data_out [7:1] = 7'b0001010;
				default : data_out [7:1] = {7{1'b0}};
			endcase
			data_out [0] = data_in [0];
		end
	end

endmodule
多路选择器
module mux(EN ,IN0 ,IN1 ,IN2 ,IN3 ,SEL ,OUT );

	input  EN ;
	input  [7:0] IN0 ,IN1 ,IN2 ,IN3 ;
	input  [1:0] SEL ;

	output [7:0] OUT ;
	reg  [7:0] OUT ;


	always @(SEL  or EN  or IN0  or IN1  or IN2  or IN3 )
	begin
		if (EN  == 0) OUT  = {8{1'b0}};
		else
			case (SEL )
				0 : OUT  = IN0 ;
				1 : OUT  = IN1 ;
				2 : OUT  = IN2 ;
				3 : OUT  = IN3 ;
				default : OUT  = {8{1'b0}};
			endcase
	end

endmodule
//-- 简单的锁存器 verilog hdl


// Latch Inference


module latchinf(enable, data, q);

input enable, data;
output q;
reg q;

always @(enable or data)
if (enable)
q <= data;

endmodule