syslib.c

来自「au1500开发的应用程序」· C语言 代码 · 共 770 行 · 第 1/2 页

/***************************************************************************
*
* sysToMonitor - transfer control to the ROM monitor
*
* This routine transfers control to the ROM monitor.  Normally, it is called
* only by reboot()--which services ^X--and bus errors at interrupt level.
* However, in some circumstances, the user may wish to introduce a
* <startType> to enable special boot ROM facilities.
*
* NOTE:
* - 
* 
* RETURNS: Does not return.
*/

STATUS sysToMonitor
    (
    int startType    /* parameter passed to ROM to tell it how to boot */
    )
    {
    FUNCPTR pRom = (FUNCPTR) (ROM_TEXT_ADRS + 8);

    (* pRom) (startType);

    return (OK);    /* in case we ever continue from rom monitor */
    }

/***************************************************************************
*
* sysClearTlb - clear the translation lookaside buffer
*
* This routine clears the entries in the translation lookaside buffer (TLB)
* for the au CPU.
*
* RETURNS: N/A
*
* NOMANUAL
*/

void sysClearTlb (void)
    {
    FAST int tlbEntry;

    for (tlbEntry = 0; tlbEntry < AU_N_TLB_ENTRIES; tlbEntry ++)
        sysClearTlbEntry (tlbEntry);

    sysWiredSet(0);

    }

/***************************************************************************
*
* sysSetTlb - add an entry to the translation lookaside buffer 
*
* This routine uses the wired register to set the next available index
* in the translation lookaside buffer (TLB)
*
* RETURNS: N/A
*
* NOMANUAL
*/

void sysSetTlb
    (
    int virtAddr,     /* 32-bit virtual address */
    int physAddr,     /* Upper 23 bits [35:12] of physical address */
    int mode	      /* Bits 28_13 for PageSize; */
    )         	  /* bits 5:0 for cache mode/enable */
    {
    int tlbRow;

    tlbRow = sysWiredGet();

    sysSetTlbEntry (virtAddr, physAddr, mode, tlbRow);

    sysWiredSet(++tlbRow);
    }

/***************************************************************************
*
* sysCacheInit - initialize the MIPS Au cache library
*
* Initializes the generic cache library to work with the MIPS Au.
*
* RETURNS: OK or ERROR
*
* NOMANUAL
*/

LOCAL STATUS sysCacheInit
    (
    CACHE_MODE instMode, 
    CACHE_MODE dataMode
    )
    {
    return cacheAuLibInit(
	instMode,	  /* I-cache mode */
	dataMode,	  /* D-cache mode */
	ICACHE_SIZE,	  /* I-cache size */
	ICACHE_LINE_SIZE, /* I-cache line size */
	DCACHE_SIZE,	  /* D-cache size */
	DCACHE_LINE_SIZE  /* D-cache line size */
	);
    }

/*******************************************************************************
*
* sysSw0Gen - generate software interrupt 0
*
* This routine writes to the MIPS cause register to generate a software
* interrupt.
*
* RETURNS: N/A
*/

void sysSw0Gen (void)
    {
    unsigned causeReg;

    causeReg = intCRGet ();
    causeReg |= CAUSE_SW1;
    intCRSet (causeReg);
    }

/*******************************************************************************
*
* sysSw1Gen - generate software interrupt 1
*
* This routine writes to the MIPS cause register to generate a software
* interrupt.
*
* RETURNS: N/A
*/

void sysSw1Gen (void)
    {
    unsigned causeReg;

    causeReg = intCRGet ();
    causeReg |= CAUSE_SW2;
    intCRSet (causeReg);
    }

/*******************************************************************************
*
* sysSw0Ack - acknowledge software interrupt 0
*
* This routine writes to the MIPS cause register to acknowledge a software
* interrupt.
*
* NOTE:
* This routine is provided as a default interrupt service routine.
*
* RETURNS: N/A
*/

LOCAL int sysSw0Ack (void)
    {
    unsigned causeReg;

    causeReg = intCRGet ();
    causeReg &= ~CAUSE_SW1;
    intCRSet (causeReg);

    return (OK);
    }

/*******************************************************************************
*
* sysSw1Ack - acknowledge software interrupt 1 
*
* This routine writes to the MIPS cause register to acknowledge a software
* interrupt.
*
* NOTE:
* This routine is provided as a default interrupt service routine.
*
* RETURNS: N/A
*/

LOCAL int sysSw1Ack (void)
    {
    unsigned causeReg;

    causeReg = intCRGet ();
    causeReg &= ~CAUSE_SW2;
    intCRSet (causeReg);

    return (OK);
    }

/******************************************************************************
*
* sysBusEid - get the value of the error ID register
*
* This routine returns the contents of the bus error status register
* MIPS devices have no such register, so they simply return zero.
*
* RETURNS: 0, always.
*/

USHORT sysBusEid (void)
    {
    return (0);
    }

/******************************************************************************
*
* sysBusEar - get the access address of a bus error
*
* This routine returns the address of a bus error.
*
* NOTE:
* This routine must be provided on all MIPS board support packages.
* MIPS devices cannot determine the address that caused
* a bus error.  It is possible to determine the source of a read bus error
* by interpreting the instruction stream that caused the bus error.
*
* RETURNS: -1, always.
*/

ULONG sysBusEar (void)
    {
    return (-1);
    }

/******************************************************************************
*
* sysMaskVmeErr - mask the VMEbus error interrupt
*
* This routine is required for all MIPS BSPs.  It has no effect.
*
* RETURNS: 0.
*
* NOMANUAL
*/

UINT8 sysMaskVmeErr (void)
    {
    return (0);
    }

/******************************************************************************
*
* sysUnmaskVmeErr - unmask the VMEbus error interrupt
*
* This routine is required for all MIPS BSPs.  It has no effect.
*
* RETURNS: 0.
*
* NOMANUAL
*/

UINT8 sysUnmaskVmeErr (void)
    {
    return (0);
    }

/******************************************************************************
*
* sysIntEnable - enable a bus interrupt level
*
* Not Implemented
*
* NOMANUAL 
*/
 
STATUS sysIntEnable
    (
    int intLevel       /* interrupt level to enable (1-7) */
    )
    {
    return (ERROR);
    }

/******************************************************************************
*
* sysIntDisable - disable a bus interrupt level
*
* Not Implemented
*
* NOMANUAL 
*/
 
STATUS sysIntDisable
    (
    int intLevel       /* interrupt level to disable (1-7) */
    )
    {
    return (ERROR);
    }

#if defined(INCLUDE_TIMESTAMP)

/***********************************************************************   
*
* sysMicroDelay - delay specific time in microsecond 
*
* This routine delay <us> microsecond. It can be called in any routine
* in non multi-tasking environment. This routine depend on timestamp.
*
* NOTE: 
* - in V100R001CPE board, the <us> must be in the range of (1us, 10s).
*
* RETURNS: OK, or ERROR if parameter out of range.
*
*/

STATUS sysMicroDelay
    (
     UINT32 us         /* micro second to delay */
    )
    {

#if 0
    UINT32 tsTicksPerUs; 
    UINT32 tsPeriod; 
    long delayTicks = 0;
    UINT32 oldMark;
    UINT32 newMark;
    int level;
    
    long temp = 0;

#if 0
    taskLock();
    level = intLock();
#endif
    
    /* const */

    tsTicksPerUs = sysTimestampFreq()/1000000;
    tsPeriod = sysTimestampPeriod();
    
    /* get start timestamp, mark it */

    oldMark = newMark = sysTimestampLock();
    
    /* check parameter */
    
    if(us > tsPeriod / tsTicksPerUs)
        return (ERROR);

    /* get delay counting ticks */

    delayTicks = us * tsTicksPerUs;

    /* polling and consuming time */

    while(delayTicks > 0)
        {

        /* get new timestamp */

        newMark = sysTimestampLock();

        /* decrement counting ticks */

	temp = (newMark > oldMark) ? (newMark - oldMark) :
                         (tsPeriod - oldMark + newMark);

        delayTicks -= temp;
        
        /* update old mark */

        oldMark = newMark;
        }

#if 0
    intUnlock(level);
    taskUnlock();
#endif    

#endif  /* not working, comment out. FIX IT */

#if defined(DELAY_US)
    DELAY_US(us);
#endif

    return OK;
    }

#endif  /* INCLUDE_TIMESTAMP */