📄 au1500int.h
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/* au1500Int.h - au1x00 Interrupt Controller */
/* Copyright 2002 Wind River Systems, Inc. */
/*
* This file has been developed or significantly modified by the
* MIPS Center of Excellence Dedicated Engineering Staff.
* This notice is as per the MIPS Center of Excellence Master Partner
* Agreement, do not remove this notice without checking first with
* WR/Platforms MIPS Center of Excellence engineering management.
*/
/*
modification history
--------------------
01a,11mar04,fhchen adopted from pb1500/au1000.h (ver 01a)
*/
#ifndef __INCau1500Inth
#define __INCau1500Inth
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Vector definitions */
#define INT_VEC_BASE 0x40 /* Base of hardware interrupt numbers */
#define INT_NUM_IC0 (INT_VEC_BASE + 8)
#define INT_NUM_IC1 (INT_VEC_BASE + 8 + 32)
/* Direct interrupt vectors */
#define IV_SW0_VEC (INT_VEC_BASE + 0) /* Software INT 0 */
#define IV_SW1_VEC (INT_VEC_BASE + 1) /* Software INT 1 */
#define IV_CTRL0_REQ0_VEC (INT_VEC_BASE + 2) /* Controller 0, Req 0 */
#define IV_CTRL0_REQ1_VEC (INT_VEC_BASE + 3) /* Controller 0, Req 1 */
#define IV_CTRL1_REQ0_VEC (INT_VEC_BASE + 4) /* Controller 1, Req 0 */
#define IV_CTRL1_REQ1_VEC (INT_VEC_BASE + 5) /* Controller 1, Req 1 */
#define IV_HW4_VEC (INT_VEC_BASE + 6) /* HW 4 */
#define IV_TIMER_VEC (INT_VEC_BASE + 7) /* Timer */
/*
* Indirect interrupt vectors:
* these vectors are to handle the muxed interrupts
*/
#define IV_IC0_REQ0 (INT_NUM_IC0 + 0)
#define IV_IC0_REQ1 (INT_NUM_IC0 + 1)
#define IV_IC0_REQ2 (INT_NUM_IC0 + 2)
#define IV_IC0_REQ3 (INT_NUM_IC0 + 3)
#define IV_IC0_REQ4 (INT_NUM_IC0 + 4)
#define IV_IC0_REQ5 (INT_NUM_IC0 + 5)
#define IV_IC0_REQ6 (INT_NUM_IC0 + 6)
#define IV_IC0_REQ7 (INT_NUM_IC0 + 7)
#define IV_IC0_REQ8 (INT_NUM_IC0 + 8)
#define IV_IC0_REQ9 (INT_NUM_IC0 + 9)
#define IV_IC0_REQ10 (INT_NUM_IC0 + 10)
#define IV_IC0_REQ11 (INT_NUM_IC0 + 11)
#define IV_IC0_REQ12 (INT_NUM_IC0 + 12)
#define IV_IC0_REQ13 (INT_NUM_IC0 + 13)
#define IV_IC0_REQ14 (INT_NUM_IC0 + 14)
#define IV_IC0_REQ15 (INT_NUM_IC0 + 15)
#define IV_IC0_REQ16 (INT_NUM_IC0 + 16)
#define IV_IC0_REQ17 (INT_NUM_IC0 + 17)
#define IV_IC0_REQ18 (INT_NUM_IC0 + 18)
#define IV_IC0_REQ19 (INT_NUM_IC0 + 19)
#define IV_IC0_REQ20 (INT_NUM_IC0 + 20)
#define IV_IC0_REQ21 (INT_NUM_IC0 + 21)
#define IV_IC0_REQ22 (INT_NUM_IC0 + 22)
#define IV_IC0_REQ23 (INT_NUM_IC0 + 23)
#define IV_IC0_REQ24 (INT_NUM_IC0 + 24)
#define IV_IC0_REQ25 (INT_NUM_IC0 + 25)
#define IV_IC0_REQ26 (INT_NUM_IC0 + 26)
#define IV_IC0_REQ27 (INT_NUM_IC0 + 27)
#define IV_IC0_REQ28 (INT_NUM_IC0 + 28)
#define IV_IC0_REQ29 (INT_NUM_IC0 + 29)
#define IV_IC0_REQ30 (INT_NUM_IC0 + 30)
#define IV_IC0_REQ31 (INT_NUM_IC0 + 31)
#define IV_IC1_REQ0 (INT_NUM_IC1 + 0)
#define IV_IC1_REQ1 (INT_NUM_IC1 + 1)
#define IV_IC1_REQ2 (INT_NUM_IC1 + 2)
#define IV_IC1_REQ3 (INT_NUM_IC1 + 3)
#define IV_IC1_REQ4 (INT_NUM_IC1 + 4)
#define IV_IC1_REQ5 (INT_NUM_IC1 + 5)
#define IV_IC1_REQ6 (INT_NUM_IC1 + 6)
#define IV_IC1_REQ7 (INT_NUM_IC1 + 7)
#define IV_IC1_REQ8 (INT_NUM_IC1 + 8)
#define IV_IC1_REQ9 (INT_NUM_IC1 + 9)
#define IV_IC1_REQ10 (INT_NUM_IC1 + 10)
#define IV_IC1_REQ11 (INT_NUM_IC1 + 11)
#define IV_IC1_REQ12 (INT_NUM_IC1 + 12)
#define IV_IC1_REQ13 (INT_NUM_IC1 + 13)
#define IV_IC1_REQ14 (INT_NUM_IC1 + 14)
#define IV_IC1_REQ15 (INT_NUM_IC1 + 15)
#define IV_IC1_REQ16 (INT_NUM_IC1 + 16)
#define IV_IC1_REQ17 (INT_NUM_IC1 + 17)
#define IV_IC1_REQ18 (INT_NUM_IC1 + 18)
#define IV_IC1_REQ19 (INT_NUM_IC1 + 19)
#define IV_IC1_REQ20 (INT_NUM_IC1 + 20)
#define IV_IC1_REQ21 (INT_NUM_IC1 + 21)
#define IV_IC1_REQ22 (INT_NUM_IC1 + 22)
#define IV_IC1_REQ23 (INT_NUM_IC1 + 23)
#define IV_IC1_REQ24 (INT_NUM_IC1 + 24)
#define IV_IC1_REQ25 (INT_NUM_IC1 + 25)
#define IV_IC1_REQ26 (INT_NUM_IC1 + 26)
#define IV_IC1_REQ27 (INT_NUM_IC1 + 27)
#define IV_IC1_REQ28 (INT_NUM_IC1 + 28)
#define IV_IC1_REQ29 (INT_NUM_IC1 + 29)
#define IV_IC1_REQ30 (INT_NUM_IC1 + 30)
#define IV_IC1_REQ31 (INT_NUM_IC1 + 31)
#if defined(AU1000)
#define IV_UART0_VEC (IV_IC0_REQ0)
#define IV_UART1_VEC (IV_IC0_REQ1)
#define IV_UART2_VEC (IV_IC0_REQ2)
#define IV_UART3_VEC (IV_IC0_REQ3)
#define IV_SSI0_VEC (IV_IC0_REQ4)
#define IV_SSI1_VEC (IV_IC0_REQ5)
#define IV_DMA0_VEC (IV_IC0_REQ6)
#define IV_DMA1_VEC (IV_IC0_REQ7)
#define IV_DMA2_VEC (IV_IC0_REQ8)
#define IV_DMA3_VEC (IV_IC0_REQ9)
#define IV_DMA4_VEC (IV_IC0_REQ10)
#define IV_DMA5_VEC (IV_IC0_REQ11)
#define IV_DMA6_VEC (IV_IC0_REQ12)
#define IV_DMA7_VEC (IV_IC0_REQ13)
#define IV_TOY_VEC (IV_IC0_REQ14)
#define IV_TOY_MATCH0_VEC (IV_IC0_REQ15)
#define IV_TOY_MATCH1_VEC (IV_IC0_REQ16)
#define IV_TOY_MATCH2_VEC (IV_IC0_REQ17)
#define IV_RTC_VEC (IV_IC0_REQ18)
#define IV_RTC_MATCH0_VEC (IV_IC0_REQ19)
#define IV_RTC_MATCH1_VEC (IV_IC0_REQ20)
#define IV_RTC_MATCH2_VEC (IV_IC0_REQ21)
#define IV_IRDA_TX_VEC (IV_IC0_REQ22)
#define IV_IRDA_RX_VEC (IV_IC0_REQ23)
#define IV_USB_DEV_IRQ_VEC (IV_IC0_REQ24)
#define IV_USB_DEV_SUSP_VEC (IV_IC0_REQ25)
#define IV_USB_HOST_VEC (IV_IC0_REQ26)
#define IV_ACSYNC_VEC (IV_IC0_REQ27)
#define IV_MAC0_DMA_VEC (IV_IC0_REQ28)
#define IV_MAC1_DMA_VEC (IV_IC0_REQ29)
#define IV_AC97_CMD_DONE_VEC (IV_IC0_REQ31)
#elif defined(AU1500)
#define IV_UART0_VEC (IV_IC0_REQ0)
#define IV_PCI_A_VEC (IV_IC0_REQ1)
#define IV_PCI_B_VEC (IV_IC0_REQ2)
#define IV_UART3_VEC (IV_IC0_REQ3)
#define IV_PCI_C_VEC (IV_IC0_REQ4)
#define IV_PCI_D_VEC (IV_IC0_REQ5)
#define IV_DMA0_VEC (IV_IC0_REQ6)
#define IV_DMA1_VEC (IV_IC0_REQ7)
#define IV_DMA2_VEC (IV_IC0_REQ8)
#define IV_DMA3_VEC (IV_IC0_REQ9)
#define IV_DMA4_VEC (IV_IC0_REQ10)
#define IV_DMA5_VEC (IV_IC0_REQ11)
#define IV_DMA6_VEC (IV_IC0_REQ12)
#define IV_DMA7_VEC (IV_IC0_REQ13)
#define IV_TOY_VEC (IV_IC0_REQ14)
#define IV_TOY_MATCH0_VEC (IV_IC0_REQ15)
#define IV_TOY_MATCH1_VEC (IV_IC0_REQ16)
#define IV_TOY_MATCH2_VEC (IV_IC0_REQ17)
#define IV_RTC_VEC (IV_IC0_REQ18)
#define IV_RTC_MATCH0_VEC (IV_IC0_REQ19)
#define IV_RTC_MATCH1_VEC (IV_IC0_REQ20)
#define IV_RTC_MATCH2_VEC (IV_IC0_REQ21)
#define IV_USB_DEV_IRQ_VEC (IV_IC0_REQ24)
#define IV_USB_DEV_SUSP_VEC (IV_IC0_REQ25)
#define IV_USB_HOST_VEC (IV_IC0_REQ26)
#define IV_ACSYNC_VEC (IV_IC0_REQ27)
#define IV_MAC0_DMA_VEC (IV_IC0_REQ28)
#define IV_MAC1_DMA_VEC (IV_IC0_REQ29)
#define IV_AC97_CMD_DONE_VEC (IV_IC0_REQ31)
#elif defined(AU1100)
#define IV_UART0_VEC (IV_IC0_REQ0)
#define IV_UART1_VEC (IV_IC0_REQ1)
#define IV_SD_VEC (IV_IC0_REQ2)
#define IV_UART3_VEC (IV_IC0_REQ3)
#define IV_SSI0_VEC (IV_IC0_REQ4)
#define IV_SSI1_VEC (IV_IC0_REQ5)
#define IV_DMA0_VEC (IV_IC0_REQ6)
#define IV_DMA1_VEC (IV_IC0_REQ7)
#define IV_DMA2_VEC (IV_IC0_REQ8)
#define IV_DMA3_VEC (IV_IC0_REQ9)
#define IV_DMA4_VEC (IV_IC0_REQ10)
#define IV_DMA5_VEC (IV_IC0_REQ11)
#define IV_DMA6_VEC (IV_IC0_REQ12)
#define IV_DMA7_VEC (IV_IC0_REQ13)
#define IV_TOY_VEC (IV_IC0_REQ14)
#define IV_TOY_MATCH0_VEC (IV_IC0_REQ15)
#define IV_TOY_MATCH1_VEC (IV_IC0_REQ16)
#define IV_TOY_MATCH2_VEC (IV_IC0_REQ17)
#define IV_RTC_VEC (IV_IC0_REQ18)
#define IV_RTC_MATCH0_VEC (IV_IC0_REQ19)
#define IV_RTC_MATCH1_VEC (IV_IC0_REQ20)
#define IV_RTC_MATCH2_VEC (IV_IC0_REQ21)
#define IV_IRDA_TX_VEC (IV_IC0_REQ22)
#define IV_IRDA_RX_VEC (IV_IC0_REQ23)
#define IV_USB_DEV_IRQ_VEC (IV_IC0_REQ24)
#define IV_USB_DEV_SUSP_VEC (IV_IC0_REQ25)
#define IV_USB_HOST_VEC (IV_IC0_REQ26)
#define IV_ACSYNC_VEC (IV_IC0_REQ27)
#define IV_MAC0_DMA_VEC (IV_IC0_REQ28)
#define IV_GPIO2XX_VEC (IV_IC0_REQ29)
#define IV_I2S_VEC (IV_IC0_REQ30)
#define IV_AC97_CMD_DONE_VEC (IV_IC0_REQ31)
#elif defined(AU1550)
#define IV_UART0_VEC (IV_IC0_REQ0)
#define IV_PCI_A_VEC (IV_IC0_REQ1)
#define IV_PCI_B_VEC (IV_IC0_REQ2)
#define IV_DDMA_VEC (IV_IC0_REQ3)
#define IV_CRYPTO_VEC (IV_IC0_REQ4)
#define IV_PCI_C_VEC (IV_IC0_REQ5)
#define IV_PCI_D_VEC (IV_IC0_REQ6)
#define IV_PCI_RESET_VEC (IV_IC0_REQ7)
#define IV_UART1_VEC (IV_IC0_REQ8)
#define IV_UART3_VEC (IV_IC0_REQ9)
#define IV_PSC0_VEC (IV_IC0_REQ10)
#define IV_PSC1_VEC (IV_IC0_REQ11)
#define IV_PSC2_VEC (IV_IC0_REQ12)
#define IV_PSC3_VEC (IV_IC0_REQ13)
#define IV_TOY_VEC (IV_IC0_REQ14)
#define IV_TOY_MATCH0_VEC (IV_IC0_REQ15)
#define IV_TOY_MATCH1_VEC (IV_IC0_REQ16)
#define IV_TOY_MATCH2_VEC (IV_IC0_REQ17)
#define IV_RTC_VEC (IV_IC0_REQ18)
#define IV_RTC_MATCH0_VEC (IV_IC0_REQ19)
#define IV_RTC_MATCH1_VEC (IV_IC0_REQ20)
#define IV_RTC_MATCH2_VEC (IV_IC0_REQ21)
#define IV_PCI_ERROR_VEC (IV_IC0_REQ22)
#define IV_NAND_VEC (IV_IC0_REQ23)
#define IV_USB_DEV_IRQ_VEC (IV_IC0_REQ24)
#define IV_USB_DEV_SUSP_VEC (IV_IC0_REQ25)
#define IV_USB_HOST_VEC (IV_IC0_REQ26)
#define IV_MAC0_DMA_VEC (IV_IC0_REQ27)
#define IV_MAC1_DMA_VEC (IV_IC0_REQ28)
#else
#error "Unsupported Au1x00 CPU"
#endif
#define IV_GPIO0_VEC (IV_IC1_REQ0)
#define IV_GPIO1_VEC (IV_IC1_REQ1)
#define IV_GPIO2_VEC (IV_IC1_REQ2)
#define IV_GPIO3_VEC (IV_IC1_REQ3)
#define IV_GPIO4_VEC (IV_IC1_REQ4)
#define IV_GPIO5_VEC (IV_IC1_REQ5)
#define IV_GPIO6_VEC (IV_IC1_REQ6)
#define IV_GPIO7_VEC (IV_IC1_REQ7)
#define IV_GPIO8_VEC (IV_IC1_REQ8)
#define IV_GPIO9_VEC (IV_IC1_REQ9)
#define IV_GPIO10_VEC (IV_IC1_REQ10)
#define IV_GPIO11_VEC (IV_IC1_REQ11)
#define IV_GPIO12_VEC (IV_IC1_REQ12)
#define IV_GPIO13_VEC (IV_IC1_REQ13)
#define IV_GPIO14_VEC (IV_IC1_REQ14)
#define IV_GPIO15_VEC (IV_IC1_REQ15)
#define IV_GPIO16_VEC (IV_IC1_REQ16)
#define IV_GPIO17_VEC (IV_IC1_REQ17)
#define IV_GPIO18_VEC (IV_IC1_REQ18)
#define IV_GPIO19_VEC (IV_IC1_REQ19)
#define IV_GPIO20_VEC (IV_IC1_REQ20)
#define IV_GPIO21_VEC (IV_IC1_REQ21)
#define IV_GPIO22_VEC (IV_IC1_REQ22)
#define IV_GPIO23_VEC (IV_IC1_REQ23)
#define IV_GPIO24_VEC (IV_IC1_REQ24)
#define IV_GPIO25_VEC (IV_IC1_REQ25)
#define IV_GPIO26_VEC (IV_IC1_REQ26)
#define IV_GPIO27_VEC (IV_IC1_REQ27)
#define IV_GPIO28_VEC (IV_IC1_REQ28)
#define IV_GPIO29_VEC (IV_IC1_REQ29)
#define IV_GPIO30_VEC (IV_IC1_REQ30)
#define IV_GPIO31_VEC (IV_IC1_REQ31)
#if defined(AU1500)
# define IV_GPIO200_VEC (IV_IC1_REQ16)
# define IV_GPIO201_VEC (IV_IC1_REQ17)
# define IV_GPIO202_VEC (IV_IC1_REQ18)
# define IV_GPIO203_VEC (IV_IC1_REQ19)
# define IV_GPIO20_VEC (IV_IC1_REQ20)
# define IV_GPIO204_VEC (IV_IC1_REQ21)
# define IV_GPIO205_VEC (IV_IC1_REQ22)
# define IV_GPIO23_VEC (IV_IC1_REQ23)
# define IV_GPIO24_VEC (IV_IC1_REQ24)
# define IV_GPIO25_VEC (IV_IC1_REQ25)
# define IV_GPIO26_VEC (IV_IC1_REQ26)
# define IV_GPIO27_VEC (IV_IC1_REQ27)
# define IV_GPIO28_VEC (IV_IC1_REQ28)
# define IV_GPIO206_VEC (IV_IC1_REQ29)
# define IV_GPIO207_VEC (IV_IC1_REQ30)
# define IV_GPIO208_VEC (IV_IC1_REQ31)
# define IV_GPIO209_VEC (IV_IC1_REQ31)
# define IV_GPIO210_VEC (IV_IC1_REQ31)
# define IV_GPIO211_VEC (IV_IC1_REQ31)
# define IV_GPIO212_VEC (IV_IC1_REQ31)
# define IV_GPIO213_VEC (IV_IC1_REQ31)
# define IV_GPIO214_VEC (IV_IC1_REQ31)
# define IV_GPIO215_VEC (IV_IC1_REQ31)
#endif
#define IV_LAST_VEC (IV_GPIO31_VEC + 1)
#define IV_ILLEGAL_VEC (INT_NUM_IC1 + 32)
/* Au1x00 Interrupt Controller Polarity Flags */
#define INT_UNDEFINED 0x0000
#define INT_TYPE_LEVEL 0x0001
#define INT_TYPE_EDGE 0x0000
#define INT_HIGH_LEVEL 0x0002
#define INT_LOW_LEVEL 0x0004
#define INT_RISING_EDGE INT_HIGH_LEVEL
#define INT_FALLING_EDGE INT_LOW_LEVEL
#define INT_REQUEST0 0x0000
#define INT_REQUEST1 0x0008
#define INT_NOWAKEUP 0x0010
#define HL (INT_TYPE_LEVEL | INT_HIGH_LEVEL)
#define LL (INT_TYPE_LEVEL | INT_LOW_LEVEL)
#define RE (INT_TYPE_EDGE | INT_RISING_EDGE)
#define FE (INT_TYPE_EDGE | INT_FALLING_EDGE)
/* Register Offsets */
#define uint32 UINT32
typedef volatile struct
{
uint32 reserved[0x40>>2];
uint32 ic_cfg0rd;
#define ic_cfg0set ic_cfg0rd
uint32 ic_cfg0clr;
uint32 ic_cfg1rd;
#define ic_cfg1set ic_cfg1rd
uint32 ic_cfg1clr;
uint32 ic_cfg2rd;
#define ic_cfg2set ic_cfg2rd
uint32 ic_cfg2clr;
#define ic_req0int ic_cfg2clr
uint32 ic_srcrd;
#define ic_srcset ic_srcrd
uint32 ic_srcclr;
#define ic_req1int ic_srcclr
uint32 ic_assignrd;
#define ic_assignset ic_assignrd
uint32 ic_assignclr;
uint32 ic_wakerd;
#define ic_wakeset ic_wakerd
uint32 ic_wakeclr;
uint32 ic_maskrd;
#define ic_maskset ic_maskrd
uint32 ic_maskclr;
uint32 ic_risingrd;
#define ic_risingclr ic_risingrd
uint32 ic_fallingrd;
#define ic_fallingclr ic_fallingrd
uint32 ic_testbit;
} AU1000_IC;
/* interface */
#ifndef _ASMLANGUAGE
void au1000IntEnable (int vector);
void au1000IntDisable (int vector);
#define au1000IntConnect(VECTOR, HANDLER, ARG, ENABLE) \
intConnect (INUM_TO_IVEC(VECTOR), HANDLER, ARG); \
if (ENABLE) au1000IntEnable(VECTOR);
#define intTypeSet(intNum, intType) (au1000IntTypeSet(intNum, intType))
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __INCau1500Inth */
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