v100r001cpe.h

au1500开发的应用程序

/* V100R001CPE.h - V100R001CPE board header */

/* Copyright 2002-2004 Founder Communications, Inc. */

/*
modification history
--------------------
01a,15mar05,fhchen  adapted from pb1500_mips32sf/pb1500.h (ver 01d)
*/

/*
DESCRIPTION

This file contains I/O addresses and related constants for the V100R001CPE
board.

*/

#ifndef __INCV100R001CPEH
#define __INCV100R001CPEH

#ifdef __cplusplus
extern "C" {
#endif	 /* __cplusplus */

#include "drv/multi/auLib.h"
#include "au1500.h"

#define BUS			BUS_TYPE_PCI

/* config reg value to be written at cold reset */

#define KSEG0_CACHE_MODE 	3            /* 3 = cached */

#if (_BYTE_ORDER == _BIG_ENDIAN)
# define INITIAL_SR             (SR_CU0 | SR_BEV) /* initial status register */
  /* default status register at task level */
# define DEFAULT_SR		(SR_CU0 | SR_IMASK0 | SR_IE)
#else
# define INITIAL_SR		(SR_CU0 | SR_BEV | SR_RE)
# define DEFAULT_SR		(SR_CU0 | SR_RE | SR_IMASK0 | SR_IE)
#endif  /* _BYTE_ORDER == _BIG_ENDIAN */

#define N_SIO_CHANNELS		2            /* Number of serial I/O channels */

#define INT_PRIO_MSB		TRUE        /* interrupt priority, msb highest */

/* TLB defines */

#define AU_N_TLB_ENTRIES	32

#define AU_TLB_16M_PGSIZE       0x01ffe000
#define AU_TLB_4M_PGSIZE        0x007fe000
#define AU_TLB_1M_PGSIZE        0x001fe000
#define AU_TLB_256K_PGSIZE      0x0007e000
#define AU_TLB_64K_PGSIZE       0x0001e000
#define AU_TLB_16K_PGSIZE       0x00006000
#define AU_TLB_4K_PGSIZE        0x00000000

#define AU_P_ENTRY_SHIFT	12 /* shift to convert VM page# to virt address */

/* To be moved to archMips.h */

#ifndef TLBLO_PFNMASK 
#define TLBLO_PFNMASK           0x3fffffc0
#define TLBLO_PFNSHIFT          6
#define TLBLO_CMASK             0x00000038
#define TLBLO_NC                0x00000010 /* uncached */
#define TLBLO_NONC              0x00000018 /* cacheable non-coherent */
#define TLBLO_CEX               0x00000020 /* cacheable coherent exclusive */
#define TLBLO_CEXW              0x00000028 /* cacheable coherent exclusive write */
#define TLBLO_CUW               0x00000030 /* cacheable coherent update write */
#define TLBLO_D                 0x4             /* writeable */
#define TLBLO_V                 0x2             /* valid bit */
#define TLBLO_G                 0x1             /* global bit */

#define TLBHI_VPN2MASK          0xffffe000
#define TLBHI_VPN2SHIFT         13
#define TLBHI_PIDMASK           0xff
#define TLBHI_PIDSHIFT          0
#define TLBHI_NPID              256
#define TLBINX_PROBE            0x80000000
#define TLBINX_INXMASK          0x0000003f
#define TLBINX_INXSHIFT         0
#define TLBRAND_RANDMASK        0x0000003f
#define TLBRAND_RANDSHIFT       0
#define TLBCTXT_BASEMASK        0xff800000
#define TLBCTXT_BASESHIFT       23
#define TLBCTXT_VPN2MASK        0x007ffff0
#define TLBCTXT_VPN2SHIFT       4
#endif /* TLBLO_PFNMASK */

/* this macro is used to generate short delays, unit is 10us */

#define DELAY(n)					  \
	li	k0, n					; \
	sll	k0, CPU_10NS_DELAY	      		; \
69:							; \
	subu	k0, 1					; \
	bnez	k0, 69b					; \
	nop

/* inaccurate delay ms */

#ifndef DELAY_MS
# define AU1500_DELAY_LOOP_MS       (CPU_MHZ * 1000)    
# define DELAY_MS(n)                                            \
     {                                                          \
     volatile int nx = 0;                                       \
     volatile int loop = (int)((n) * AU1500_DELAY_LOOP_MS);     \
     for(nx = 0; nx < loop; nx++);                              \
     }
#endif  /* DELAY_MS */

/* inaccurate delay us */

#ifndef DELAY_US
# define AU1500_DELAY_LOOP_US       CPU_MHZ    
# define DELAY_US(n)                                            \
     {                                                          \
     volatile int nx = 0;                                       \
     volatile int loop = (int)((n) * AU1500_DELAY_LOOP_US);     \
     for(nx = 0; nx < loop; nx++);                              \
     }
#endif  /* DELAY_US */    

/* inaccurate delay 10ns, assuming 400MHz */

#ifndef DELAY_10NS
# define AU1500_DELAY_LOOP_10NS       4    
# define DELAY_10NS(n)                                          \
     {                                                          \
     volatile int nx = 0;                                       \
     volatile int loop = (int)((n) * AU1500_DELAY_LOOP_10NS);   \
     for(nx = 0; nx < loop; nx++);                              \
     }
#endif  /* DELAY_10NS */

/* definitions for sys_endian register */

#if (_BYTE_ORDER == _BIG_ENDIAN)
# define ENDIAN_MODE	0
#else
# define ENDIAN_MODE	1
#endif  /* _BYTE_ORDER == _BIG_ENDIAN */

/* Byte & word swaps */

#if (_BYTE_ORDER == _BIG_ENDIAN)
/* swap byte within a word */
#define PBYTESWAP(x)		(MSB(x) | (LSB(x) << 8))
#define PSWAP(x)		LONGSWAP(x)	/* swap the long word */
#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
#define PBYTESWAP(x)		(x)
#define PSWAP(x)		(x)
#endif /* _BYTE_ORDER == _BIG_ENDIAN */

#ifdef __cplusplus
}
#endif  /* __cplusplus */
#endif  /* __INCV100R001CPEH */