au1500int.c

au1500开发的应用程序

/* au1500Int.c - Au1x00 Interrupt Handling */

/*
 * This file has been developed or significantly modified by the
 * MIPS Center of Excellence Dedicated Engineering Staff.
 * This notice is as per the MIPS Center of Excellence Master Partner
 * Agreement, do not remove this notice without checking first with
 * WR/Platforms MIPS Center of Excellence engineering management.
 */

/* Copyright 2002 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01a,11mar05,fhchen  adopted from pb1500/au1000Int.c (ver 01a)
*/

/*
DESCRIPTION

This library provides interrupt handling routines for AU1x00.

*/

/* includes */

#include "vxWorks.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "intLib.h"
#include "version.h"
#include "config.h"
#include "arch/mips/taskMipsLib.h"

#include "au1500.h"
#include "au1500Int.h"

/* externals */

IMPORT UINT8    ffsMsbTbl[];            /* Msb high interrupt hash table */
IMPORT UINT8    ffsLsbTbl[];            /* Lsb high interrupt hash table */

/*
 * Since tying interrupt lines to the processor is board dependent 
 * sysHashOrder is provided to select the prioritization of interrupt lines.  
 * Setting the #define INT_PRIO_MSB to TRUE prioritizes interrupts from 7-0,
 * 7 being highest priority, 0 being lowest.  Setting it to FALSE prioritizes
 * interrupts from 0-7.  See V100R001CPE.h for the definition of INT_PRIO_MSB.
 */

#if     (INT_PRIO_MSB == TRUE)
UINT8 * sysHashOrder = ffsMsbTbl;       /* interrupt prio., 7 = high 0 = low*/
#else   /* INT_PRIO_MSB == TRUE */
UINT8 * sysHashOrder = ffsLsbTbl;       /* interrupt prio., 0 = high 7 = low*/
#endif  /* INT_PRIO_MSB == TRUE */

/* locals */

LOCAL AU1000_IC * const ic0 = (AU1000_IC *)0xB0400000;
LOCAL AU1000_IC * const ic1 = (AU1000_IC *)0xB1800000;
/* LOCAL AU1000_SYS * const sys = (AU1000_SYS *)0xB1900000; */

/* extern */

IMPORT AU1500_SYS * const sys;

/* defines */

LOCAL unsigned char intTypes[64] =
    {
#if defined(AU1000)
    /* IC0.0  UART0   */ HL,
    /* IC0.1  UART1   */ HL,
    /* IC0.2  UART2   */ HL,
    /* IC0.3  UART3   */ HL,
    /* IC0.4  SSI0    */ HL,
    /* IC0.5  SSI1    */ HL,
    /* IC0.6  DMA0    */ HL,
    /* IC0.7  DMA1    */ HL,
    /* IC0.8  DMA2    */ HL,
    /* IC0.9  DMA3    */ HL,
    /* IC0.10 DMA4    */ HL,
    /* IC0.11 DMA5    */ HL,
    /* IC0.12 DMA6    */ HL,
    /* IC0.13 DMA7    */ HL,
    /* IC0.14 TOYtick */ RE,
    /* IC0.15 TOYm0   */ RE,
    /* IC0.16 TOYm1   */ RE,
    /* IC0.17 TOYm2   */ RE,
    /* IC0.18 RTCtick */ RE,
    /* IC0.19 RTCm0   */ RE,
    /* IC0.20 RTCm1   */ RE,
    /* IC0.21 RTCm2   */ RE,
    /* IC0.22 IrDA Tx */ HL,
    /* IC0.23 IrDA Rx */ HL,
    /* IC0.24 USBd    */ HL,
    /* IC0.25 USBd Sus*/ RE,
    /* IC0.26 USBH    */ LL,
    /* IC0.27 AC97 ACS*/ RE,
    /* IC0.28 MAC0    */ HL,
    /* IC0.29 MAC1    */ HL,
    /* IC0.30 Reserved*/ 0,
    /* IC0.31 AC97 Cmd*/ RE,

#elif defined(AU1500)
    /* IC0.0  UART0   */ HL,
    /* IC0.1  INTA#   */ LL,
    /* IC0.2  INTB#   */ LL,
    /* IC0.3  UART3   */ HL,
    /* IC0.4  INTC#   */ LL,
    /* IC0.5  INTD#   */ LL,
    /* IC0.6  DMA0    */ HL,
    /* IC0.7  DMA1    */ HL,
    /* IC0.8  DMA2    */ HL,
    /* IC0.9  DMA3    */ HL,
    /* IC0.10 DMA4    */ HL,
    /* IC0.11 DMA5    */ HL,
    /* IC0.12 DMA6    */ HL,
    /* IC0.13 DMA7    */ HL,
    /* IC0.14 TOYtick */ RE,
    /* IC0.15 TOYm0   */ RE,
    /* IC0.16 TOYm1   */ RE,
    /* IC0.17 TOYm2   */ RE,
    /* IC0.18 RTCtick */ RE,
    /* IC0.19 RTCm0   */ RE,
    /* IC0.20 RTCm1   */ RE,
    /* IC0.21 RTCm2   */ RE,
    /* IC0.22 PCIerr# */ LL,
    /* IC0.23         */ 0,
    /* IC0.24 USBd    */ HL,
    /* IC0.25 USBd Sus*/ RE,
    /* IC0.26 USBH    */ LL,
    /* IC0.27 AC97 ACS*/ RE,
    /* IC0.28 MAC0    */ HL,
    /* IC0.29 MAC1    */ HL,
    /* IC0.30 Reserved*/ 0,
    /* IC0.31 AC97 Cmd*/ RE,

#elif defined(AU1100)
    /* IC0.0  UART0   */ HL,
    /* IC0.1  UART1   */ HL,
    /* IC0.2  SD0&1   */ HL,
    /* IC0.3  UART3   */ HL,
    /* IC0.4  SSI0    */ HL,
    /* IC0.5  SSI1    */ HL,
    /* IC0.6  DMA0    */ HL,
    /* IC0.7  DMA1    */ HL,
    /* IC0.8  DMA2    */ HL,
    /* IC0.9  DMA3    */ HL,
    /* IC0.10 DMA4    */ HL,
    /* IC0.11 DMA5    */ HL,
    /* IC0.12 DMA6    */ HL,
    /* IC0.13 DMA7    */ HL,
    /* IC0.14 TOYtick */ RE,
    /* IC0.15 TOYm0   */ RE,
    /* IC0.16 TOYm1   */ RE,
    /* IC0.17 TOYm2   */ RE,
    /* IC0.18 RTCtick */ RE,
    /* IC0.19 RTCm0   */ RE,
    /* IC0.20 RTCm1   */ RE,
    /* IC0.21 RTCm2   */ RE,
    /* IC0.22 IrDA Tx */ HL,
    /* IC0.23 IrDA Rx */ HL,
    /* IC0.24 USBd    */ HL,
    /* IC0.25 USBd Sus*/ RE,
    /* IC0.26 USBH    */ LL,
    /* IC0.27 AC97 ACS*/ RE,
    /* IC0.28 MAC0    */ HL,
    /* IC0.29 GPIO2   */ 0, /* app-specific */
    /* IC0.30 I2S     */ HL,
    /* IC0.31 AC97 Cmd*/ RE,

#elif defined(AU1550)
    /* IC0.0  UART0   */ HL,
    /* IC0.1  INTA#   */ LL,
    /* IC0.2  INTB#   */ LL,
    /* IC0.3  DDMA    */ HL,
    /* IC0.4  Crypto  */ HL,
    /* IC0.5  INTC#   */ LL,
    /* IC0.6  INTD#   */ LL,
    /* IC0.7  PCIReset*/ LL,
    /* IC0.8  UART1   */ HL,
    /* IC0.9  UART3   */ HL,
    /* IC0.10 PSC0    */ HL,
    /* IC0.11 PSC1    */ HL,
    /* IC0.12 PSC2    */ HL,
    /* IC0.13 PSC3    */ HL,
    /* IC0.14 TOYtick */ RE,
    /* IC0.15 TOYm0   */ RE,
    /* IC0.16 TOYm1   */ RE,
    /* IC0.17 TOYm2   */ RE,
    /* IC0.18 RTCtick */ RE,
    /* IC0.19 RTCm0   */ RE,
    /* IC0.20 RTCm1   */ RE,
    /* IC0.21 RTCm2   */ RE,
    /* IC0.22 PCIerr# */ HL,
    /* IC0.23 NAND    */ RE,
    /* IC0.24 USBd    */ HL,
    /* IC0.25 USBd Sus*/ RE,
    /* IC0.26 USBH    */ LL,
    /* IC0.27 MAC0    */ HL,
    /* IC0.28 MAC1    */ HL,
    /* IC0.29 Reserved*/ 0,
    /* IC0.30 Reserved*/ 0,
    /* IC0.31 Reserved*/ 0,

#else
#error "Unsupport Au1x00 CPU"
#endif

    /* IC1.x Application Specific */

/* V100R001CPE */

    /* IC1.0  GPIO0   */ LL, /* DSP */
    /* IC1.1  GPIO1   */ 0,
    /* IC1.2  GPIO2   */ 0,
    /* IC1.3  GPIO3   */ 0,
    /* IC1.4  GPIO4   */ 0,
    /* IC1.5  GPIO5   */ 0,
    /* IC0.6  GPIO6   */ 0,
    /* IC1.7  GPIO7   */ 0,
    /* IC1.8  GPIO8   */ 0,
    /* IC1.9  GPIO9   */ 0,
    /* IC1.10 GPIO10  */ LL, /* FPGA */
    /* IC1.11 GPIO11  */ 0,
    /* IC1.12 GPIO12  */ 0,
    /* IC1.13 GPIO13  */ 0,
    /* IC1.14 GPIO14  */ 0,
    /* IC1.15 GPIO15  */ 0,
    /* IC1.16 GPIO200 */ 0,
    /* IC1.17 GPIO201 */ 0,
    /* IC1.18 GPIO202 */ 0,
    /* IC1.19 GPIO203 */ 0,
    /* IC1.20 GPIO20  */ 0,
    /* IC1.21 GPIO204 */ 0,
    /* IC1.22 GPIO205 */ 0,
    /* IC1.23 GPIO23  */ 0,
    /* IC1.24 GPIO24  */ 0,
    /* IC1.25 GPIO25  */ 0,
    /* IC1.26 GPIO26  */ 0,
    /* IC1.27 GPIO27  */ 0,
    /* IC1.28 GPIO28  */ 0,
    /* IC1.29 GPIO206 */ 0,
    /* IC1.30 GPIO207 */ 0,
    /* IC1.31 >GPIO208 */ 0
    } ;

/* macros */

/* convert vector number to interrupt controller number and bit */

#define VEC_TO_IC_BIT(VECTOR)                                   \
    {                                                           \
    if ((VECTOR >= INT_NUM_IC0) && (VECTOR < INT_NUM_IC1))      \
        {                                                       \
        ic = ic0;                                               \
        bit = VECTOR - INT_NUM_IC0;                             \
        }                                                       \
    else if ((VECTOR >= INT_NUM_IC1) && (VECTOR < IV_LAST_VEC)) \
        {                                                       \
        ic = ic1;                                               \
        bit = VECTOR - INT_NUM_IC1;                             \
        }                                                       \
    else                                                        \
        return;                                                 \
    }

/* forward declaration */

LOCAL int sysCtrl0Req0IntDemux (int arg);
LOCAL int sysCtrl0Req1IntDemux (int arg);
LOCAL int sysCtrl1Req0IntDemux (int arg);
LOCAL int sysCtrl1Req1IntDemux (int arg);

/***************************************************************************/

/*
 *  This table is critical to interrupt processing.  Do not alter its
 *  contents until you understand the consequences. Refer to the Tornado
 *  for MIPS Architecture supplement for instructions on its use.
 */

typedef struct 
    {
    ULONG	intCause;		/* cause of interrupt	*/
    ULONG	bsrTableOffset; 	/* index to BSR table	*/
    ULONG	statusReg;		/* mask bit */
    ULONG	pad;			/* intNum or demux routine? */
    } PRIO_TABLE;

PRIO_TABLE intPrioTable[] = 
    {
	{CAUSE_SW1,(ULONG) IV_SWTRAP0_VEC,	0x0100, 0}, /* sw trap 0 */
	{CAUSE_SW2,(ULONG) IV_SWTRAP1_VEC,	0x0200, 0}, /* sw trap 1 */
	{CAUSE_IP3,(ULONG) sysCtrl0Req0IntDemux,0x0400, 1}, /* DeMultiplex */
	{CAUSE_IP4,(ULONG) sysCtrl0Req1IntDemux,0x0800, 1}, /* DeMultiplex */
	{CAUSE_IP5,(ULONG) sysCtrl1Req0IntDemux,0x1000, 1}, /* DeMultiplex */
	{CAUSE_IP6,(ULONG) sysCtrl1Req1IntDemux,0x2000, 1}, /* DeMultiplex */
	{CAUSE_IP7,(ULONG) IV_HW4_VEC,		0x4000, 0}, /* Available */
	{CAUSE_IP8,(ULONG) IV_TIMER_VEC, 	0x8000, 0}  /* Timer share */
    };

/***************************************************************************
 *
 * au1500IntTypeSet - configure individual interrupt polarities
 *
 * NOTE:
 * 
 * RETURNS: N/A
 */

LOCAL void au1500IntTypeSet
(
    int vector, /* interrupt number/vector to set */
    int flags   /* type/flag to set */
    )
    {
    AU1000_IC *ic;
    int bit;

    VEC_TO_IC_BIT(vector);