au1500.h

au1500开发的应用程序

/* au1500.h - common au1x00 header */

/* Copyright 2002 Wind River Systems, Inc. */

/*
 * This file has been developed or significantly modified by the
 * MIPS Center of Excellence Dedicated Engineering Staff.
 * This notice is as per the MIPS Center of Excellence Master Partner
 * Agreement, do not remove this notice without checking first with
 * WR/Platforms MIPS Center of Excellence engineering management.
 */

/*
modification history
--------------------
01a,11mar05,fhchen  adopted from pb1500/au1x00Lib.h (ver 01a)
*/

/*
DESCRIPTION

This file contains I/O addresses and related constants for the
Alchemy Semiconductor(Now AMD) Au1x00 MIPS processors.
*/

#ifndef __INCau1500h
#define __INCau1500h

#ifdef __cplusplus
extern "C" {
#endif	 /* __cplusplus */

/* includes */

#include "drv/multi/auLib.h"
#include "arch/mips/archMips.h"
#include "arch/mips/taskMipsLib.h"

/* Physical base addresses for integrated peripherals */

#ifdef AU1000
#define	MEM_PHYS_ADDR		0x14000000
#define	DMA0_PHYS_ADDR		0x14002000
#define	DMA1_PHYS_ADDR		0x14002100
#define	DMA2_PHYS_ADDR		0x14002200
#define	DMA3_PHYS_ADDR		0x14002300
#define	DMA4_PHYS_ADDR		0x14002400
#define	DMA5_PHYS_ADDR		0x14002500
#define	DMA6_PHYS_ADDR		0x14002600
#define	DMA7_PHYS_ADDR		0x14002700
#define	IC0_PHYS_ADDR		0x10400000
#define	IC1_PHYS_ADDR		0x11800000
#define	AC97_PHYS_ADDR		0x10000000
#define	USBH_PHYS_ADDR		0x10100000
#define	USBD_PHYS_ADDR		0x10200000
#define	IRDA_PHYS_ADDR		0x10300000
#define	MAC0_PHYS_ADDR		0x10500000
#define	MAC1_PHYS_ADDR		0x10510000
#define	MACEN_PHYS_ADDR		0x10520000
#define	MACDMA0_PHYS_ADDR	0x14004000
#define	MACDMA1_PHYS_ADDR	0x14004200
#define	I2S_PHYS_ADDR		0x11000000
#define	UART0_PHYS_ADDR		0x11100000
#define	UART1_PHYS_ADDR		0x11200000
#define	UART2_PHYS_ADDR		0x11300000
#define	UART3_PHYS_ADDR		0x11400000
#define	SSI0_PHYS_ADDR		0x11600000
#define	SSI1_PHYS_ADDR		0x11680000
#define	SYS_PHYS_ADDR		0x11900000
#endif

#ifdef AU1500
#define	MEM_PHYS_ADDR		0x14000000
#define	DMA0_PHYS_ADDR		0x14002000
#define	DMA1_PHYS_ADDR		0x14002100
#define	DMA2_PHYS_ADDR		0x14002200
#define	DMA3_PHYS_ADDR		0x14002300
#define	DMA4_PHYS_ADDR		0x14002400
#define	DMA5_PHYS_ADDR		0x14002500
#define	DMA6_PHYS_ADDR		0x14002600
#define	DMA7_PHYS_ADDR		0x14002700
#define	IC0_PHYS_ADDR		0x10400000
#define	IC1_PHYS_ADDR		0x11800000
#define	AC97_PHYS_ADDR		0x10000000
#define	USBH_PHYS_ADDR		0x10100000
#define	USBD_PHYS_ADDR		0x10200000
#define	IRDA_PHYS_ADDR		0x10300000
#define	MAC0_PHYS_ADDR		0x11500000
#define	MAC1_PHYS_ADDR		0x11510000
#define	MACEN_PHYS_ADDR		0x11520000
#define	MACDMA0_PHYS_ADDR	0x14004000
#define	MACDMA1_PHYS_ADDR	0x14004200
#define	I2S_PHYS_ADDR		0x11000000
#define	UART0_PHYS_ADDR		0x11100000
#define	UART3_PHYS_ADDR		0x11400000
#define	SSI0_PHYS_ADDR		0x11600000
#define	SSI1_PHYS_ADDR		0x11680000
#define GPIO2_PHYS_ADDR		0x11700000
#define	SYS_PHYS_ADDR		0x11900000
#endif

#ifdef AU1100
#define	MEM_PHYS_ADDR		0x14000000
#define	DMA0_PHYS_ADDR		0x14002000
#define	DMA1_PHYS_ADDR		0x14002100
#define	DMA2_PHYS_ADDR		0x14002200
#define	DMA3_PHYS_ADDR		0x14002300
#define	DMA4_PHYS_ADDR		0x14002400
#define	DMA5_PHYS_ADDR		0x14002500
#define	DMA6_PHYS_ADDR		0x14002600
#define	DMA7_PHYS_ADDR		0x14002700
#define	IC0_PHYS_ADDR		0x10400000
#define	IC1_PHYS_ADDR		0x11800000
#define	AC97_PHYS_ADDR		0x10000000
#define	USBH_PHYS_ADDR		0x10100000
#define	USBD_PHYS_ADDR		0x10200000
#define	IRDA_PHYS_ADDR		0x10300000
#define	MAC0_PHYS_ADDR		0x10500000
#define	MACEN_PHYS_ADDR		0x10520000
#define	MACDMA0_PHYS_ADDR	0x14004000
#define	MACDMA1_PHYS_ADDR	0x14004200
#define	I2S_PHYS_ADDR		0x11000000
#define	UART0_PHYS_ADDR		0x11100000
#define	UART1_PHYS_ADDR		0x11200000
#define	UART3_PHYS_ADDR		0x11400000
#define	SSI0_PHYS_ADDR		0x11600000
#define	SSI1_PHYS_ADDR		0x11680000
#define	SYS_PHYS_ADDR		0x11900000
#define LCD_PHYS_ADDR		0x15000000
#endif /* AU1100 */

#ifdef AU1550
#define	MEM_PHYS_ADDR		0x14000000
#define	IC0_PHYS_ADDR		0x10400000
#define	IC1_PHYS_ADDR		0x11800000
#define	USBH_PHYS_ADDR		0x10100000
#define	USBD_PHYS_ADDR		0x10200000
#define	MAC0_PHYS_ADDR		0x10500000
#define	MAC1_PHYS_ADDR		0x10510000
#define	MACEN_PHYS_ADDR		0x10520000
#define	MACDMA0_PHYS_ADDR	0x14004000
#define	MACDMA1_PHYS_ADDR	0x14004200
#define	UART0_PHYS_ADDR		0x11100000
#define	UART1_PHYS_ADDR		0x11200000
#define	UART3_PHYS_ADDR		0x11400000
#define GPIO2_PHYS_ADDR		0x11700000
#define	SYS_PHYS_ADDR		0x11900000
#endif /* AU1550 */    

/* static memory bit defines */

#define	AU1500_STIME_TWCS(x)	((x) << 28)
#define	AU1500_STIME_TCSH(x)	((x) << 24)
#define	AU1500_STIME_TWP(x)	((x) << 14)
#define	AU1500_STIME_TCSW(x)	((x) << 10)
#define	AU1500_STIME_TPM(x)	((x) << 6)
#define	AU1500_STIME_TA(x)	((x) << 0)

#define	AU1500_STCONFIG_BE	(1 << 9)
#define	AU1500_STCONFIG_EW	(1 << 7)
#define AU1500_STCONFIG_H       (1 << 6)
#define AU1500_DTY_SRAM		0
#define AU1500_DTY_IO		1
#define AU1500_DTY_PCMCIA	2
#define AU1500_DTY_FLASH	3
#define AU1500_DTY_LCD		4

/* Addresses of the base MAC registers */

#define AU_MAC0_REG_BASE        PHYS_TO_K1(0x11500000)
#define AU_MAC0_DMA_BASE        PHYS_TO_K1(0x14004000)
#define AU_MAC0_ENABLE          PHYS_TO_K1(0x11520000)
#define AU_MAC1_REG_BASE        PHYS_TO_K1(0x11510000)
#define AU_MAC1_DMA_BASE        PHYS_TO_K1(0x14004200)
#define AU_MAC1_ENABLE          PHYS_TO_K1(0x11520004)

#ifndef _ASMLANGUAGE
typedef volatile struct
{
	/* 0x0000 */ UINT32 sys_toytrim;
	/* 0x0004 */ UINT32 sys_toywrite;
	/* 0x0008 */ UINT32 sys_toymatch0;
	/* 0x000C */ UINT32 sys_toymatch1;
	/* 0x0010 */ UINT32 sys_toymatch2;
	/* 0x0014 */ UINT32 sys_cntrctrl;
	/* 0x0018 */ UINT32 sys_scratch0;
	/* 0x001C */ UINT32 sys_scratch1;
	/* 0x0020 */ UINT32 sys_freqctrl0;
	/* 0x0024 */ UINT32 sys_freqctrl1;
	/* 0x0028 */ UINT32 sys_clksrc;
	/* 0x002C */ UINT32 sys_pinfunc;
	/* 0x0030 */ UINT32 reserved0;
	/* 0x0034 */ UINT32 sys_wakemsk;
	/* 0x0038 */ UINT32 sys_endian;
	/* 0x003C */ UINT32 sys_powerctrl;
	/* 0x0040 */ UINT32 sys_toyread;
	/* 0x0044 */ UINT32 sys_rtctrim;
	/* 0x0048 */ UINT32 sys_rtcwrite;
	/* 0x004C */ UINT32 sys_rtcmatch0;
	/* 0x0050 */ UINT32 sys_rtcmatch1;
	/* 0x0054 */ UINT32 sys_rtcmatch2;
	/* 0x0058 */ UINT32 sys_rtcread;
	/* 0x005C */ UINT32 sys_wakesrc;
	/* 0x0060 */ UINT32 sys_cpupll;
	/* 0x0064 */ UINT32 sys_auxpll;
	/* 0x0068 */ UINT32 reserved1;
	/* 0x006C */ UINT32 reserved2;
	/* 0x0070 */ UINT32 reserved3;
	/* 0x0074 */ UINT32 reserved4;
	/* 0x0078 */ UINT32 sys_slppwr;
	/* 0x007C */ UINT32 sys_sleep;
	/* 0x0080 */ UINT32 reserved5[32];
	/* 0x0100 */ UINT32 sys_trioutrd;
#define sys_trioutclr sys_trioutrd
	/* 0x0104 */ UINT32 reserved6;
	/* 0x0108 */ UINT32 sys_outputrd;
#define sys_outputset sys_outputrd
	/* 0x010C */ UINT32 sys_outputclr;
	/* 0x0110 */ UINT32 sys_pinstaterd;
#define sys_pininputen sys_pinstaterd

    } AU1000_SYS, AU1500_SYS;
#endif
    
#ifdef __cplusplus
}
#endif  /* __cplusplus */
#endif  /* __INCau1500h */