📄 rominit.s
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/* romInit.s - V100R001CPE ROM initialization module */
/* Copyright 2002-2004 Founder Communications, Inc. */
.data
.globl copyright_wind_river
/*
* This file has been developed or significantly modified by the
* MIPS Center of Excellence Dedicated Engineering Staff.
* This notice is as per the MIPS Center of Excellence Master Partner
* Agreement, do not remove this notice without checking first with
* WR/Platforms MIPS Center of Excellence engineering management.
*/
/*
modification history
--------------------
01a,04apr05,fhchen written from pb1500_mips32sf/romInit.s (ver 01b)
*/
/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
The routine sysToMonitor() jumps to romInit() to perform a
"warm boot".
*/
#define _ASMLANGUAGE
/* includes */
#include "vxWorks.h"
#include "sysLib.h"
#include "cacheLib.h"
#include "config.h"
#include "asm.h"
#include "esf.h"
/* defines */
/*
* Configure the CONFIG register
*
* This macro configures the K0 field of the config register
* by ORing the KSEG0_CACHE_MODE value in V100R001CPE.h with the
* already existing config register value.
*
* It also determines the endian mode for which the kernel was compiled.
* This requires the following 4 step process:
* 1. Set sys_endian register to desired mode.
* 2. Read sys_endian register
* 3. Read CP0 CONFIG0 register
* 4. Write CP0 CONFIG0 register
*
*/
#define CONFIG_INIT \
.set noreorder ; \
mfc0 t0, C0_CONFIG ; \
HAZARD_CP_READ ; \
and t0, ~0x07 ; \
or t0, KSEG0_CACHE_MODE; \
mtc0 t0, C0_CONFIG ; \
HAZARD_CP_WRITE ; \
li t0, ENDIAN_MODE ; \
sw t0, AU_SYS_ENDIAN ; \
lw t0, AU_SYS_ENDIAN ; \
mfc0 t0, C0_CONFIG ; \
HAZARD_CP_READ ; \
mtc0 t0, C0_CONFIG ; \
HAZARD_CP_WRITE ; \
.set reorder
#define ROM_ISP_BASE 0xa0010000
#include "romMipsInit.s"
/***************************************************************************
*
* romTextUpdate - do cache-text-update from bootApp
*
* Tail-call to au1x00 cache routine, as we don't need to allocate a stack.
*
*/
.ent romTextUpdate
romTextUpdate:
li a0, ICACHE_SIZE
li a1, ICACHE_LINE_SIZE
li a2, DCACHE_SIZE
li a3, DCACHE_LINE_SIZE
la t0, cacheAuRomTextUpdate
j t0
.end romTextUpdate
/***************************************************************************
*
* romClearEdac - clear error detection and correction logic
*
* This routine clears the memory and error detection logic by
* doing word writes to each DRAM location.
*/
.ent romClearEdac
romClearEdac:
mfc0 v1, C0_SR
#if FALSE
or v0, v1, SR_DE /* disable parity errors, N/A in AU1500 */
mtc0 v0, C0_SR
#endif
/* If ECC supported, use LOCAL_MEM_SIZE, else use RAM_LOW_ADRS */
li a0, (K1BASE | RAM_LOW_ADRS)
clearloop:
sw zero, -4(a0)
sw zero, -8(a0)
sw zero, -12(a0)
sw zero, -16(a0)
sw zero, -20(a0)
sw zero, -24(a0)
sw zero, -28(a0)
sw zero, -32(a0)
sw zero, -36(a0)
sw zero, -40(a0)
sw zero, -44(a0)
sw zero, -48(a0)
sw zero, -52(a0)
sw zero, -56(a0)
sw zero, -60(a0)
sw zero, -64(a0)
subu a0, 64
bne a0, K1BASE, clearloop
done:
mtc0 v1, C0_SR
j ra
.end romClearEdac
/***************************************************************************
*
* romExcHandle - rom based exception/interrupt handler
*
* This routine is invoked on an exception or interrupt while
* the status register is using the bootstrap exception vectors.
* It saves a state frame to a known uncached location.
*
* THIS ROUTIINE IS NOT CALLABLE FROM "C"
*
*/
.ent romExcHandle
romExcHandle:
.set noat
li sp, ROM_ISP_BASE /* sp to known uncached location */
SW sp, E_STK_SP-ESTKSIZE(sp) /* save sp in new intstk frame */
subu sp, ESTKSIZE /* make new exc stk frame */
SW k0, E_STK_K0(sp) /* save k0, (exception type) */
SW AT, E_STK_AT(sp) /* save asmbler resvd reg */
.set at
SW v0, E_STK_V0(sp) /* save func return 0, used */
/* to hold masked cause */
mfc0 k1, C0_BADVADDR /* read bad VA reg */
sw k1, E_STK_BADVADDR(sp) /* save bad VA on stack */
mfc0 k1, C0_EPC /* read exception pc */
sw k1, E_STK_EPC(sp) /* save EPC on stack */
mfc0 v0, C0_CAUSE /* read cause register */
sw v0, E_STK_CAUSE(sp) /* save cause on stack */
mfc0 k1, C0_SR /* read status register */
sw k1, E_STK_SR(sp) /* save status on stack */
.set noat
mflo AT /* read entry lo reg */
SW AT, E_STK_LO(sp) /* save entry lo reg */
mfhi AT /* read entry hi reg */
SW AT, E_STK_HI(sp) /* save entry hi reg */
.set at
SW zero, E_STK_ZERO(sp) /* save zero ?! */
SW v1, E_STK_V1(sp) /* save func return 1 */
SW a0, E_STK_A0(sp) /* save passed param 0 */
SW a1, E_STK_A1(sp) /* save passed param 1 */
SW a2, E_STK_A2(sp) /* save passed param 2 */
SW a3, E_STK_A3(sp) /* save passed param 3 */
SW t0, E_STK_T0(sp) /* save temp reg 0 */
SW t1, E_STK_T1(sp) /* save temp reg 1 */
SW t2, E_STK_T2(sp) /* save temp reg 2 */
SW t3, E_STK_T3(sp) /* save temp reg 3 */
SW t4, E_STK_T4(sp) /* save temp reg 4 */
SW t5, E_STK_T5(sp) /* save temp reg 5 */
SW t6, E_STK_T6(sp) /* save temp reg 6 */
SW t7, E_STK_T7(sp) /* save temp reg 7 */
SW t8, E_STK_T8(sp) /* save temp reg 8 */
SW t9, E_STK_T9(sp) /* save temp reg 9 */
SW s0, E_STK_S0(sp) /* save saved reg 0 */
SW s1, E_STK_S1(sp) /* save saved reg 1 */
SW s2, E_STK_S2(sp) /* save saved reg 2 */
SW s3, E_STK_S3(sp) /* save saved reg 3 */
SW s4, E_STK_S4(sp) /* save saved reg 4 */
SW s5, E_STK_S5(sp) /* save saved reg 5 */
SW s6, E_STK_S6(sp) /* save saved reg 6 */
SW s7, E_STK_S7(sp) /* save saved reg 7 */
SW s8, E_STK_FP(sp) /* save saved reg 8 */
SW gp, E_STK_GP(sp) /* save global pointer? */
SW ra, E_STK_RA(sp) /* save return address */
1:
b 1b /* Infinite Loop */
.end romExcHandle /* that's all folks */
/******************************************************************************
*
* sysMemInit - Initialize BSP memory
*
* This routine performs any BSP-specific memory initialization required in the
* common romInit routine. This routine is called from Assembly code and ROM,
* and does not use any local RAM.
*
* RETURNS: N/A
*
* NOMANUAL
* void sysMemInit (void)
*/
.ent sysMemInit
sysMemInit:
staticRamInit:
#if defined(RCS0_IS_28F128J3) && defined(RCS3_IS_28F128J3)
#error sysMemInit: invalid static bus scheme
#endif
#if defined(RCS0_IS_29LV040) && !defined(RCS0_IS_28F128J3)
/*---------------------------------------------------------
* RCS0: 1MB, 16-bit socket Flash (AM29LV040 * 2)
* mem_stcfg0: 16 bit flash
* mem_sttime0: using those for pb1500 BSP
* mem_staddr0: 1FC00000-1FCFFFFF
*--------------------------------------------------------*/
li t1, (AU1500_DTY_FLASH | AU1500_STCONFIG_H)
#if (_BYTE_ORDER == _BIG_ENDIAN)
or t1, AU1500_STCONFIG_BE
#endif
sw t1, AU_STATIC_CONFIG(0)
li t1, (AU1500_STIME_TWCS(0x02) | AU1500_STIME_TCSH(0x02) | \
AU1500_STIME_TWP(0x20) | AU1500_STIME_TCSW(0x02) | \
AU1500_STIME_TPM(0x0C) | AU1500_STIME_TA(0x20))
sw t1, AU_STATIC_TIMING(0)
li t1, (SET_STATIC_ADDRESS_CSADDR(0x07F0) | \
SET_STATIC_ADDRESS_AMASK(0x3FFC) | \
AU_STATIC_ADDRESS_E)
sw t1, AU_STATIC_ADDRESS(0)
#elif defined(RCS0_IS_28F128J3) && !defined(RCS0_IS_29LV040)
/*---------------------------------------------------------
* RCS0: 16MB, 16-bit on board Flash (28F128J3)
* mem_stcfg0: 16 bit flash
* mem_sttime0: using those for pb1500 BSP
* mem_staddr0: 1F000000-1FFFFFFF
*--------------------------------------------------------*/
li t1, (AU1500_DTY_FLASH | AU1500_STCONFIG_H)
#if (_BYTE_ORDER == _BIG_ENDIAN)
or t1, AU1500_STCONFIG_BE
#endif
sw t1, AU_STATIC_CONFIG(0)
li t1, (AU1500_STIME_TWCS(0x02) | AU1500_STIME_TCSH(0x02) | \
AU1500_STIME_TWP(0x20) | AU1500_STIME_TCSW(0x02) | \
AU1500_STIME_TPM(0x0C) | AU1500_STIME_TA(0x20))
sw t1, AU_STATIC_TIMING(0)
li t1, (SET_STATIC_ADDRESS_CSADDR(0x07C0) | \
SET_STATIC_ADDRESS_AMASK(0x3FC0) | \
AU_STATIC_ADDRESS_E)
sw t1, AU_STATIC_ADDRESS(0)
#else
# error sysMemInit: invalid RCS0 scheme
#endif /* defined(RCS0_IS_28F128J3) && !defined(RCS0_IS_29LV040) */
/*---------------------------------------------------------
* RCS1: 16KB, 32-bit Static RAM(TMS320C6410)
* mem_stcfg1: 32 bit SRAM
* mem_sttime1: using those for pb1500 BSP
* mem_staddr1: 03000000-03003FFF,
* (A7 and A6 is HCNTL[1..0])
*--------------------------------------------------------*/
li t1, AU1500_DTY_SRAM
#if (_BYTE_ORDER == _BIG_ENDIAN)
or t1, AU1500_STCONFIG_BE
#endif
sw t1, AU_STATIC_CONFIG(1)
li t1, (AU1500_STIME_TWCS(0x02) | AU1500_STIME_TCSH(0x02) | \
AU1500_STIME_TWP(0x20) | AU1500_STIME_TCSW(0x02) | \
AU1500_STIME_TPM(0x08) | AU1500_STIME_TA(0x20))
sw t1, AU_STATIC_TIMING(1)
li t1, (SET_STATIC_ADDRESS_CSADDR(0x00C0) | \
SET_STATIC_ADDRESS_AMASK(0x3FFF) | \
AU_STATIC_ADDRESS_E)
sw t1, AU_STATIC_ADDRESS(1)
/*---------------------------------------------------------
* RCS2: 256B, 12-bit Static RAM(FPGA)
* mem_stcfg2: 16 bit SRAM
* mem_sttime2: using those for pb1500 BSP
* mem_staddr2: 1D000000-1D0000FF
*--------------------------------------------------------*/
li t1, (AU1500_DTY_SRAM | AU1500_STCONFIG_H)
#if (_BYTE_ORDER == _BIG_ENDIAN)
or t1, AU1500_STCONFIG_BE
#endif
sw t1, AU_STATIC_CONFIG(2)
li t1, (AU1500_STIME_TWCS(0x02) | AU1500_STIME_TCSH(0x02) | \
AU1500_STIME_TWP(0x20) | AU1500_STIME_TCSW(0x02) | \
AU1500_STIME_TPM(0x08) | AU1500_STIME_TA(0x20))
sw t1, AU_STATIC_TIMING(2)
li t1, (SET_STATIC_ADDRESS_CSADDR(0x0740) | \
SET_STATIC_ADDRESS_AMASK(0x3FFF) | \
AU_STATIC_ADDRESS_E)
sw t1, AU_STATIC_ADDRESS(2)
#if defined(RCS3_IS_28F128J3)
/*---------------------------------------------------------
* RCS3: 16MB, 16-bit on board Flash (28F128J3)
* mem_stcfg3: 16 bit flash
* mem_sttime3: using those for pb1500 BSP
* mem_staddr3: 1E000000-1EFFFFFF
*--------------------------------------------------------*/
li t1, (AU1500_DTY_FLASH | AU1500_STCONFIG_H)
#if (_BYTE_ORDER == _BIG_ENDIAN)
or t1, AU1500_STCONFIG_BE
#endif
sw t1, AU_STATIC_CONFIG(3)
li t1, (AU1500_STIME_TWCS(0x02) | AU1500_STIME_TCSH(0x02) | \
AU1500_STIME_TWP(0x20) | AU1500_STIME_TCSW(0x02) | \
AU1500_STIME_TPM(0x0c) | AU1500_STIME_TA(0x20))
sw t1, AU_STATIC_TIMING(3)
li t1, (SET_STATIC_ADDRESS_CSADDR(0x0780) | \
SET_STATIC_ADDRESS_AMASK(0x3FC0) | \
AU_STATIC_ADDRESS_E)
sw t1, AU_STATIC_ADDRESS(3)
#elif defined(RCS3_IS_NONE)
#endif /* defined(RCS3_IS_28F128J3) */
sdRamInit:
/* wait around 100 ns before setup */
DELAY(10)
/*---------------------------------------------------------
* SDCS0: 32MB, 32-bit on board SDRAM (MT48LC8M32B2TG-6)
* mem_sdmode0: 4 banks, Row 12, Column 9
* mem_sdaddr0: 00000000-01FFFFFF
* mem_sdrefcfg: 64ms, 4096 cycle refresh (15.6us/row),
* 400MHz system bus, Trc and Trpm using
* those for pb1500 BSP
* mem_sdwrmd0: CAS latency 2(consistent with that in
* mem_sdmode0[Tcl]), burst length 8
*--------------------------------------------------------*/
/* timing cycles */
li t1, (AU_SDRAM_CS_MODE_F | AU_SDRAM_CS_MODE_BS | \
SET_SDRAM_CS_MODE_RS(1) | SET_SDRAM_CS_MODE_CS(2) | \
SET_SDRAM_CS_MODE_TRAS(4)| SET_SDRAM_CS_MODE_TMRD(1)| \
SET_SDRAM_CS_MODE_TWR(1) | SET_SDRAM_CS_MODE_TRP(1) | \
SET_SDRAM_CS_MODE_TRCD(1)| SET_SDRAM_CS_MODE_TCL(1))
sw t1, AU_SDRAM_CS_MODE_0
/* base address and size */
li t1, (SET_SDRAM_CS_CONFIG_CSBA(0x00) | \
SET_SDRAM_CS_CONFIG_CSMASK(0x3F8)| \
AU_SDRAM_CS_CONFIG_E)
sw t1, AU_SDRAM_CS_CONFIG_0
/* refresh, precharge and auto refresh registers */
li t1, (SET_SDRAM_REFRESH_CONFIG_TRC(7) | \
SET_SDRAM_REFRESH_CONFIG_TRPR(1) | \
SET_SDRAM_REFRESH_CONFIG_REF_INTER(0x186A))
sw t1, AU_SDRAM_REFRESH_CONFIG
sw zero, AU_SDRAM_PRECHARGE_CMD
sw zero, AU_SDRAM_AUTO_REFRESH_CMD
li t1, (SET_SDRAM_REFRESH_CONFIG_TRC(7) | \
SET_SDRAM_REFRESH_CONFIG_TRPR(1) | \
SET_SDRAM_REFRESH_CONFIG_REF_INTER(0x186A) | \
AU_SDRAM_REFRESH_CONFIG_E)
sw t1, AU_SDRAM_REFRESH_CONFIG
/* external SDRAM mode register */
li t1, 0x23
sw t1, AU_SDRAM_WRITE_EXTERN_0
/* wait around 100 ns after setup */
DELAY(10)
j ra
.end sysMemInit
/******************************************************************************
*
* sysCacheInit - Initialize BSP cache
*
* This routine performs any BSP-specific cache initialization required in the
* common romInit routine. This routine is called from assembly code and ROM,
* and does not use any local RAM.
*
* RETURNS: N/A
*
* NOMANUAL
* void sysCacheInit (void)
*/
.ent sysCacheInit
sysCacheInit:
/* Save return address */
move s1, ra
#if FALSE
li t0, ICACHE_SIZE
li t1, ICACHE_LINE_SIZE
li t2, DCACHE_SIZE
li t3, DCACHE_LINE_SIZE
move a0, s0 /* start type */
RELOC(v0, cacheAuReset)
jal v0
#endif
/* Restore return address */
move ra, s1
j ra
.end sysCacheInit
/******************************************************************************
*
* sysLedErr - indicating error using led.
*
* This routine is required by romMipsInit.s after kernel startup failure
*
* RETURNS: N/A
*
* NOMANUAL
* void sysLedErr (void)
*/
.ent sysLedErr
sysLedErr:
j ra
.end sysLedErr
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